Z8F4801AN020SC Zilog, Z8F4801AN020SC Datasheet - Page 149
Z8F4801AN020SC
Manufacturer Part Number
Z8F4801AN020SC
Description
IC ENCORE MCU FLASH 48K 44-LQFP
Manufacturer
Zilog
Series
Encore!®r
Specifications of Z8F4801AN020SC
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
269-3142
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Table 79. DMA_ADC Status Register (DMAA_STAT)
PS017610-0404
RESET
FIELD
ADDR
BITS
R/W
DMA Status Register
R
7
0
The DMA Status register indicates the DMA channel that generated the interrupt and the
ADC Analog Input that is currently undergoing conversion. Reads from this register reset
the Interrupt Request Indicator bits (IRQA, IRQ1, and IRQ0) to 0. Therefore, software
interrupt service routines that read this register must process all three interrupt sources
from the DMA.
CADC[3:0]—Current ADC Analog Input
This field identifies the Analog Input that the ADC is currently converting.
Reserved
This bit is reserved and must be 0.
IRQA—DMA_ADC Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA_ADC is not the source of the interrupt from the DMA Controller.
1 = DMA_ADC completed transfer of data from the last ADC Analog Input and generated
an interrupt.
IRQ1—DMA1 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA1 is not the source of the interrupt from the DMA Controller.
1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt.
IRQ0—DMA0 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA0 is not the source of the interrupt from the DMA Controller.
1 = DMA0 completed transfer of data to/from the End Address and generated an interrupt.
R
6
0
CADC[3:0]
R
5
0
R
4
0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
FBFH
Reserved
R
3
0
Direct Memory Access Controller
IRQA
R
2
0
IRQ1
1
R
0
Z8 Encore!
IRQ0
R
0
0
®
131
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