Z8F4801AN020SC Zilog, Z8F4801AN020SC Datasheet - Page 137
Z8F4801AN020SC
Manufacturer Part Number
Z8F4801AN020SC
Description
IC ENCORE MCU FLASH 48K 44-LQFP
Manufacturer
Zilog
Series
Encore!®r
Specifications of Z8F4801AN020SC
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
269-3142
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Manufacturer
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Price
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Table 68. I
PS017609-0803
RESET
FIELD
ADDR
BITS
R/W
I
2
2
C Control Register
C Control Register (I2CCTL)
R/W
IEN
7
0
received a byte of data. When active, this bit causes the I
interrupt. This bit is cleared by reading the I
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge was received for the last byte transmitted
or received.
10B—10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit
is set, if the five most-significant bits of the address are 11110B, this bit is set. When set,
it is reset once the first byte of the address has been sent.
RD—Read
This bit indicates the direction of transfer of the data. It is active high during a read. The
status of this bit is determined by the least-significant bit of the I
START bit is set.
TAS—Transmit Address State
This bit is active high while the address is being shifted out of the I
DSS—Data Shift State
This bit is active high while data is being transmitted to or from the I
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only
be cleared by setting the START or STOP bit, allowing the user to specify whether he
wants to perform a STOP or a repeated START.
The I
IEN—I
This bit enables the I
2
C Control register enables the I
2
C Enable
START
R/W
6
0
2
STOP
R/W
C transmitter and receiver.
5
0
BIRQ
R/W
4
0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
2
C operation.
F52H
2
C Data register.
R/W
TXI
3
0
2
C Controller to generate an
NAK
R/W
2
0
2
C Shift register after the
2
C Shift register.
FLUSH
2
C Shift register.
R/W
1
0
Z8 Encore!
I2C Controller
FILTEN
R/W
0
0
®
119
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