AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 202
AT89C51SND2C-7FTUL
Manufacturer Part Number
AT89C51SND2C-7FTUL
Description
IC 8051 MCU FLASH 64K MP3 100BGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51SND2C-7FTUL.pdf
(242 pages)
Specifications of AT89C51SND2C-7FTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b; D/A 2x20b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
ATAPI, I2S, IDE, SPI, UART, USB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT89C51SND2C7FTUL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51SND2C-7FTUL
Manufacturer:
ATMEL
Quantity:
4 371
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Registers
AT8xC51SND2C/MP3B
enabled by setting EADC bit in IEN1 register. This flag is set by hardware and must be reset by
software.
Table 3. ADCON Register
ADCON (S:F3h) – ADC Control Register
Reset Value = 0000 0000b
Table 4. ADCLK Register
ADCLK (S:F2h) – ADC Clock Divider Register
Reset Value = 0000 0000b
Bit Number
Bit Number
2 - 1
7 - 5
4 - 0
7
7
6
5
4
3
0
7
-
-
Mnemonic
Mnemonic
ADCD4:0
ADEOC
ADSST
ADIDL
ADIDL
ADEN
ADCS
Bit
Bit
6
6
-
-
-
-
Description
Reserved
The value read from this bit is always 0. Do not set this bit.
ADC Pseudo-Idle Mode
Set to suspend the CPU core activity (pseudo-idle mode) during conversion.
Clear by hardware at the end of conversion.
ADC Enable Bit
Set to enable the A to D converter.
Clear to disable the A to D converter and put it in low power stand by mode.
End Of Conversion Flag
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
Must be cleared by software.
Start and Status Bit
Set to start an A to D conversion on the selected channel.
Cleared by hardware at the end of conversion.
Reserved
The value read from these bits is always 0. Do not set these bits.
Channel Selection Bit
Set to select channel 0 for conversion.
Clear to select channel 1 for conversion.
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
ADC Clock Divider
5-bit divider for ADC clock generation.
ADEN
5
5
-
ADEOC
ADCD4
4
4
ADCD3
ADSST
3
3
ADCD2
2
2
-
ADCD1
1
1
-
4341H–MP3–10/07
ADCD0
ADCS
0
0
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