AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 156
AT89C51SND2C-7FTUL
Manufacturer Part Number
AT89C51SND2C-7FTUL
Description
IC 8051 MCU FLASH 64K MP3 100BGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51SND2C-7FTUL.pdf
(242 pages)
Specifications of AT89C51SND2C-7FTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b; D/A 2x20b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
ATAPI, I2S, IDE, SPI, UART, USB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT89C51SND2C7FTUL
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51SND2C-7FTUL
Manufacturer:
ATMEL
Quantity:
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19. Synchronous Peripheral Interface
Figure 19-1. Typical Master SPI Bus Configuration
Figure 19-2. Typical Slave SPI Bus Configuration
156
AT8xC51SND2C/MP3B
AT8xC51SND2C
MASTER
The AT8xC51SND2C implements a Synchronous Peripheral Interface with master and slave
modes capability.
Figure 19-1 shows an SPI bus configuration using the AT8xC51SND2C as master connected to
slave peripherals while Figure 19-2 shows an SPI bus configuration using the AT8xC51SND2C
as slave of an other master.
The bus is made of three wires connecting all the devices together:
•
•
•
Each slave peripheral is selected by one Slave Select pin (SS). If there is only one slave, it may
be continuously selected with SS tied to a low level. Otherwise, the AT8xC51SND2C may select
each device by software through port pins (Pn.x). Special care should be taken not to select 2
slaves at the same time to avoid bus conflicts.
MISO
MOSI
SCK
SSn
SS1
SS0
P4.0
P4.1
P4.2
Pn.z
Pn.y
Pn.x
Master Output Slave Input (MOSI): it is used to transfer data in series from the master to a
slave.
It is driven by the master.
Master Input Slave Output (MISO): it is used to transfer data in series from a slave to the
master.
It is driven by the selected slave.
Serial Clock (SCK): it is used to synchronize the data transmission both in and out the
devices through their MOSI and MISO lines. It is driven by the master for eight clock cycles
which allows to exchange one Byte on the serial lines.
MISO
MOSI
SCK
SS
SS
SO
SO
DataFlash 1
Slave 1
SI
SI
SCK
SCK
SS
SS
SO
SO
DataFlash 2
Slave 2
SI
SI
SCK
SCK
MISO MOSI SCK
SS
AT8xC51SND2C
SS
SO
Slave n
Controller
SI
LCD
SCK
4341H–MP3–10/07
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