AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet
AT89C51SND2C-7FTUL
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AT89C51SND2C-7FTUL Summary of contents
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... Bytes of Code Memory – AT89C51SND2C and 89SND2CMP3B: Flash (100K Erase/Write Cycles) – AT83SND2C and 83SND2CMP3B: ROM • 4K Bytes of Boot Flash Memory (AT89C51SND2C and 89SND2CMP3B) – ISP: Download from USB (standard) or UART (option) • USB Rev 1.1 Controller – Full Speed Data Transmission • ...
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... C51 microcontroller core handling data flow, MP3-player control, Stereo Audio DAC and Mono Audio Power Amplifier for speaker control. The AT89C51SND2C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash memory. The AT83SND2C includes 64K Bytes of ROM memory. ...
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Block Diagram Figure 3-1. AT8xC51SND2C / AT8XSND2CMP3B Block Diagram ISP FILT Clock and PLL X1 X2 RST D+ D- P0-P4 DOUT DCLK DSEL SCLK HSR HSL AUXP AUXN LINEL LINER MONOP MONON PAINP PAINN HPP HPN 3 Alternate function ...
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... P3.4/ LINER DSEL RXD T0 P3.5/ X1 DCLK TST T1 P3.6/ P3.7/ VSS LPHN RD WR P3.3/ AUDVBAT AUDVSS HPN INT1 1. ISP pin is only available in AT89C51SND2C product. Do not connect this pin on AT83SND2C product Not Connect AUXP AUXN ALE P0.0/ ISP/ B KIN0 AD0 NC P0.1/ P0. AD1 AD2 ...
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Figure 4- P4.0/ P2.2/ P2.1/ MISO A10 A9 P2.0/ P2.4/ P2.3/ A8 A12 A11 P4.1/ P2.5/ VDD MOSI A13 P2.6/ P2.7/ VSS A14 A15 EA VDD FILT MDAT MCLK MCMD SCLK AUDRST RST DCLK DOUT DSEL ...
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Signals All the AT8xC51SND2C and AT8XSND2CMP3B signals are detailed by functionality in Table Table 14. Table 4-1. Signal Name P0.7:0 P2.7:0 P3.7:0 P4.3:0 Table 4-2. Signal Name X1 X2 FILT Table 4-3. Signal Name INT0 AT8xC51SND2C/MP3B ...
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Signal Name INT1 T0 T1 Table 4-4. Signal Name DCLK DOUT DSEL SCLK Table 4-5. Signal Name D+ D- Table 4-6. Signal Name MCLK MCMD MDAT 4341H–MP3–10/07 Type Description Timer 1 Gate Input INT1 serves as external run control for ...
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Table 4-7. Signal Name RXD TXD Table 4-8. Signal Name MISO MOSI SCK SS Table 4-9. Signal Name SCL SDA Table 4-10. Signal Name KIN0 AT8xC51SND2C/MP3B 8 UART Signal Description Type Description Receive Serial Data I/O RXD sends and receives ...
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... ALE signals the start of an external bus cycle and indicates that valid address O information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. ISP Enable Input (AT89C51SND2C Only) I/O This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader. ...
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Table 4-14. Signal Name VDD VSS ADCVDD ADCVSS PVDD PVSS UVDD UVSS Table 4-15. Signal Name AUDVDD AUDVSS ESDVSS AUDVREF HSVDD HSVSS AUDVBAT Table 4-16. Signal Name LPHN HPN HPP CBP AT8xC51SND2C/MP3B 10 Power Signal Description Type Description Digital Supply ...
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Signal Name PAINN PAINP AUDRST MONON MONOP AUXP AUXN HSL HSR LINEL LINER INGND AUDVCM 4341H–MP3–10/07 Type Description I Audio Amplifier Negative Input I Audio Amplifier Positive Input I Audio Reset (Active Low) O Audio Negative Monaural Driver Output O ...
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Internal Pin Structure Table 4-17. Latch Output Notes: AT8xC51SND2C/MP3B 12 Detailed Internal Pin Structure (1) Circuit VDD VDD Watchdog Output P VSS VDD 2 osc periods VSS VDD P N VSS VDD P N VSS ...
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Clock Controller The AT8xC51SND2C clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. 5.1 Oscillator The AT8xC51SND2C X1 and ...
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... The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see on page 22). Using the AT89C51SND2C (Flash Version) the system can boot either in stan- dard or X2 mode depending on the X2B value. Using AT83SND2C (ROM Version) the system always boots in standard mode. X2B bit can be changed to X2 mode later by software. ...
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Figure 5-4. Figure 5-5. 5.3.2 PLL Programming The PLL is programmed using the flow shown in Figure 5-6. As soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure the clock output ...
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... Registers Table 5-1. 7 TWIX2 Bit Number Reset Value = 0000 000Xb (AT89C51SND2C) or 0000 0000b (AT83SND2C) Table 5- Bit Number AT8xC51SND2C/MP3B 16 CKCON Register CKCON (S:8Fh) – Clock Control Register WDX2 - SIX2 Bit Mnemonic Description Two-Wire Clock Control Bit TWIX2 Set to select the oscillator clock divided TWI clock input (X2 independent). ...
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Bit Number 1 0 Reset Value = 0000 1000b Table 5-3. PLLNDIV (S:EEh) – PLL N Divider Register 7 - Bit Number Reset Value = 0000 0000b Table 5-4. PLLRDIV (S:EFh) – PLL R Divider Register ...
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... The AT83SND2C product provides the internal program/code memory in ROM memory while the AT89C51SND2C product provides it in Flash memory. These 2 products do not allow exter- nal code memory execution. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming ...
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... This space can only be read or written by hardware mode using a parallel programming tool. 4341H–MP3–10/07 AT83SND2C Memory Architecture FFFFh 64K Bytes ROM Memory 0000h Figure 6-3 the AT89C51SND2C Flash memory is composed of four spaces detailed AT89C51SND2C Memory Architecture Hardware Security Extra Row FFFFh 64K Bytes User Flash Memory ...
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... This Byte is used to lock the execution of some boot loader commands. 6.3 Hardware Security System The AT89C51SND2C implements three lock bits LB2:0 in the LSN of HSB (see Table 6-3) pro- viding three levels of security for user’s program as described in AT83SND2C is always set in read disabled mode. ...
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... See Section “Reset Recommendation to Prevent Flash Corruption”, page 48. 4341H–MP3–10/07 RESET Hard Cond? ISP = L? Prog Cond? BLJB = P? Standard Init Prog Cond Init ENBOOT = 0 ENBOOT = 0000h PC = F000h FCON = F0h FCON = F0h User’s Atmel’s Application Boot Loader AT8xC51SND2C/MP3B Hard Cond Init ENBOOT = F000h FCON = 00h 21 ...
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... This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. - Reserved for Data Pointer Extension. Data Pointer Select Bit DPS Set to select second data pointer: DPTR1. Clear to select first data pointer: DPTR0. 1. ENBOOT bit is only available in AT89C51SND2C product. HSB Byte – Hardware Security Byte BLJB - ...
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... Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase. 4341H–MP3–10/07 1. X2B initializes the X2 bit in CKCON during the reset phase order to ensure boot loader activation at first power-up, AT89C51SND2C products are deliv- ered with BLJB programmed. 3. Bits (LSN) can only be programmed by hardware mode. ...
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Data Memory The AT8xC51SND2C provides data memory access in 2 different spaces: 1. The internal space mapped in three separate segments: – – – 2. The external space. A fourth internal segment is available but dedicated to Special Function ...
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The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. ...
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Figure 7-3 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 7-3 describes the exter- nal memory interface signals. Figure 7-3. Table 7-3. ...
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X2 mode. For further information on X2 mode, refer to the Section “X2 Feature”, page 14. Slow peripherals can be accessed by stretching the read and write cycles. This is done ...
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DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table used to ...
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Registers Table 7- Bit Number Reset Value = 0000 0000b Table 7- Bit Number 4341H–MP3–10/07 PSW Register PSW (S:D0h) ...
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Bit Number 1 0 Reset Value = X000 1101b AT8xC51SND2C/MP3B 30 Bit Mnemonic Description External RAM Enable Bit Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR EXTRAM instructions. Clear to select the internal expanded RAM ...
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... Power Control AUXR 8Eh Auxiliary Register 0 AUXR1 A2h Auxiliary Register 1 NVERS FBh Version Number Note: 1. ENBOOT bit is only available in AT89C51SND2C product. Table 8-3. PLL and System Clock SFRs Mnemonic Add Name CKCON 8Fh Clock Control PLLCON E9h PLL Control PLLNDIV ...
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... AUXCON 90h Auxiliary Control Table 8-7. Flash Memory SFR Mnemonic Add Name (1) FCON D1h Flash Control Note: 1. FCON register is only available in AT89C51SND2C product. Table 8-8. Timer SFRs Mnemonic Add Name TCON 88h Timer/Counter 0 and 1 Control TMOD 89h Timer/Counter 0 and 1 Modes TL0 ...
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Table 8-9. MP3 Decoder SFRs (Continued) Mnemonic Add Name MP3DAT ACh MP3 Data MP3ANC ADh MP3 Ancillary Data MP3VOL 9Eh MP3 Audio Volume Control Left MP3VOR 9Fh MP3 Audio Volume Control Right MP3BAS B4h MP3 Audio Bass Control MP3MED B5h ...
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Table 8-12. MMC Controller SFRs Mnemonic Add Name MMCON0 E4h MMC Control 0 MMCON1 E5h MMC Control 1 MMCON2 E6h MMC Control 2 MMSTA DEh MMC Control and Status MMINT E7h MMC Interrupt MMMSK DFh MMC Interrupt Mask DD MMCMD ...
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Table 8-16. Two Wire Controller SFRs Mnemonic Add Name SSCON 93h Synchronous Serial Control SSSTA 94h Synchronous Serial Status SSDAT 95h Synchronous Serial Data SSADR 96h Synchronous Serial Address Table 8-17. Keyboard Interface SFRs Mnemonic Add Name KBCON A3h Keyboard ...
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... Reserved Notes: 1. SFR registers with least significant nibble address equal are bit-addressable. 2. NVERS reset value depends on the silicon version: 1000 0100 for AT89C51SND2C product and 0000 0001 for AT83SND2C product. 3. FCON register is only available in AT89C51SND2C product. 4. FCON reset value is 00h in case of reset with hardware condition. ...
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Interrupt System The AT8xC51SND2C, like other control-oriented computer architectures, employ a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where ...
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Table 9-2. A low-priority interrupt is always interrupted by a higher priority interrupt but not by another inter- rupt of lower or equal priority. Higher priority interrupts are serviced before lower priority interrupts. The response to simultaneous occurrence of equal ...
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Figure 9-1. Interrupt Control System External INT0 Interrupt 0 Timer 0 External INT1 Interrupt 1 Timer 1 TXD Serial Port RXD MP3 Decoder Audio Interface MCLK MMC MDAT Controller MCMD SCL TWI Controller SDA SCK SPI SI Controller SO A ...
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External Interrupts 9.2.1 INT1:0 Inputs External interrupts INT0 and INT1 (INTn pins may each be programmed to be level- triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn ...
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Registers Table 9- Bit Number Reset Value = 0000 0000b 4341H–MP3–10/07 IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register EAUD EMP3 ES Bit Mnemonic Description ...
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Table 9- Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 42 IEN1 Register IEN1 (S:B1h) – Interrupt Enable Register EUSB - EKB Bit Mnemonic Description Reserved ...
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Table 9- Bit Number Reset Value = X000 0000b 4341H–MP3–10/07 IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register IPHAUD IPHMP3 IPHS Bit Mnemonic Description Reserved ...
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Table 9- Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 44 IPH1 Register IPH1 (S:B3h) – Interrupt Priority High Register IPHUSB - IPHKB Bit Mnemonic Description ...
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Table 9- Bit Number Reset Value = X000 0000b 4341H–MP3–10/07 IPL0 Register IPL0 (S:B8h) - Interrupt Priority Low Register IPLAUD IPLMP3 IPLS Bit Mnemonic Description Reserved ...
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Table 9- Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 46 IPL1 Register IPL1 (S:B2h) – Interrupt Priority Low Register IPLUSB - IPLKB Bit Mnemonic Description ...
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Power Management 2 power reduction modes are implemented in the AT8xC51SND2C: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and ...
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To determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. different oscillator startup and V Table 10-2. Oscillator Start-Up Time Note: 10.1.2 Warm Reset To achieve a valid reset, the reset signal ...
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Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, pro- gram execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked ...
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Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND2C enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. ...
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Notes: 10.5 Registers Table 10-3. PCON (S:87h) – Power Configuration Register 7 SMOD1 Bit Number Reset Value = 00XX 0000b 4341H–MP3–10/07 A logic high on the RST pin clears PD ...
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Timers/Counters The AT8xC51SND2C implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer event Counter. When operating ...
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Figure 11-1. Timer 0 and Timer 1 Clock Controller and Symbols PER CLOCK OSC ÷ 2 CLOCK CKCON.1 TIM0 CLOCK Timer 0 Clock Symbol 11.3 Timer 0 Timer 0 functions as either a Timer or event Counter in four modes ...
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Figure 11-3. Mode 0 Overflow Period Formula 11.3.2 Mode 1 (16-bit Timer) Mode 1 configures Timer 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 11-4). The selected input increments TL0 register. Figure 11-5 ...
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Mode 3 (2 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 11-8). This mode is provided for applications requiring an additional 8-bit Timer or Counter. TL0 uses ...
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When Timer mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate ...
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Registers Table 11-1. TCON (S:88h) – Timer/Counter Control Register 7 TF1 Bit Number Reset Value = 0000 0000b 4341H–MP3–10/07 TCON Register TR1 TF0 TR0 Bit Mnemonic Description Timer ...
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GATE1 Bit Number Notes: Reset Value = 0000 0000b Table 11-2. TH0 (S:8Ch) – Timer 0 High Byte Register 7 - Bit Number 7:0 Reset Value = 0000 0000b Table 11-3. ...
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TL0 (S:8Ah) – Timer 0 Low Byte Register 7 - Bit Number 7:0 Reset Value = 0000 0000b Table 11-4. TH1 (S:8Dh) – Timer 1 High Byte Register 7 - Bit Number 7:0 Reset Value = 0000 0000b Table 11-5. ...
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Watchdog Timer The AT8xC51SND2C implement a hardware Watchdog Timer (WDT) that automatically resets the chip allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software ...
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Watchdog Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST register. As soon enabled, there is no way except the chip reset to disable ...
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Registers Table 12-2. WDTRST (S:A6h Write only) – Watchdog Timer Reset Register 7 - Bit Number Reset Value = XXXX XXXXb Figure 12-4. WDTPRG Register WDTPRG (S:A7h) – Watchdog Timer Program Register 7 - Bit Number ...
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MP3 Decoder The AT8xC51SND2C implement a MPEG I/II audio layer 3 decoder better known as MP3 decoder. In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 kHz. Among ...
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MP3 Data The MP3 decoder does not start any frame decoding before having a complete frame in its input (1) buffer consisting of data request and data acknowledgment is implemented. Each time the MP3 decoder needs MP3 data, it ...
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Audio Controls 13.2.1 Volume Control The MP3 decoder implements volume control on both right and left channels. The MP3VOR and MP3VOL registers allow a 32-step volume control according to Table 13-2. Table 13-2. 13.2.2 Equalization Control Sound can be ...
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CRC Error When the CRC of a frame does not match the one calculated, the flag ERRCRC in MP3STA is set. In this case, depending on the CRCEN bit in MP3CON, the frame is played or rejected. In both ...
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All interrupt flags but MPANC are cleared when reading MP3STA register. The MPANC flag is cleared by hardware when the ancillary buffer becomes empty.. Figure 13-5. MP3 Decoder Interrupt System 4341H–MP3–10/07 MPANC MP3STA.7 MSKANC MP3CON.4 MPREQ MP3STA.6 MSKREQ MP3CON.3 ERRLAY ...
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Management Reading the MP3STA register automatically clears the interrupt flags (acknowledgment) except the MPANC flags. This implies that register content must be saved and tested, interrupt flag by interrupt flag to be sure not to forget any interrupts. Figure ...
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Registers Table 13-5. 7 MPEN Bit Number Reset Value = 0011 1111b 4341H–MP3–10/07 MP3CON Register MP3CON (S:AAh) – MP3 Decoder Control Register MPBBST CRCEN MSKANC Bit Mnemonic Description ...
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Table 13-6. 7 MPANC Bit Number Reset Value = 0000 0001b Table 13-7. 7 MPD7 Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 70 MP3STA Register MP3STA (S:C8h ...
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Table 13- Bit Number Reset Value = 0001 0001b Table 13-9. 7 AND7 Bit Number Reset Value = 0000 0000b Table 13-10. MP3VOL Register 7 - Bit ...
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Table 13-11. MP3VOR Register 7 - Bit Number Reset Value = 0000 0000b Table 13-12. MP3BAS Register 7 - Bit Number Reset Value = 0000 0000b Table 13-13. ...
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Table 13-14. MP3TRE Register 7 - Bit Number 4-0 Reset Value = 0000 0000b Table 13-15. MP3CLK Register 7 - Bit Number 4-0 Reset Value = 0000 0000b 4341H–MP3–10/07 MP3TRE (S:B6h) – MP3 Treble ...
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Audio Output Interface The AT8xC51SND2C implement an audio output interface allowing the audio bitstream to be output in various formats compatible with right and left justification PCM and I and thanks to the on-chip PLL (see Section ...
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Clock Generator The audio interface clock is generated by division of the PLL clock. The division factor is given by AUCD4:0 bits in CLKAUD register. Figure 14-2 shows the audio interface clock generator and its calculation formula. The audio ...
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Figure 14-4. Audio Output Format DSEL DCLK 1 2 DOUT LSB MSB B14 DSEL DCLK 1 2 DOUT MSB B14 DSEL DCLK 1 2 DOUT MSB B14 DSEL DCLK 1 DOUT DSEL DCLK 1 DOUT MSB B16 The data converter ...
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Table 14-2. DUP1 14.5 MP3 Buffer In song playing mode, the audio stream comes from the MP3 decoder through a buffer. The MP3 buffer is used to store the decoded MP3 data and interfaces to the ...
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Figure 14-6. MP3 Mode Audio Configuration Flow 14.8 Registers Table 14-3. AUDCON0 (S:9Ah) – Audio Interface Control Register 0 7 JUST4 Bit Number Reset Value = 0000 1000b Table 14-4. AUDCON1 (S:9Bh) – Audio ...
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Bit Number Reset Value = 1011 0010b Table 14-5. 7 SREQ Bit Number Reset Value = 1100 0000b 4341H–MP3–10/07 Bit Mnemonic Description MP3 Decoded Data Request ...
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Table 14-6. 7 AUD7 Bit Number Reset Value = 1111 1111b Table 14- Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 80 AUDDAT Register AUDDAT (S:9Dh) – Audio Interface ...
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DAC and PA Interface The AT8xC51SND2C implements a stereo Audio Digital-to-Analog Converter and Audio Power Amplifier targeted for Li-Ion or Ni-Mh battery powered devices. Figure 15-1. Audio Interface Block Diagram 15.1 DAC The Stereo DAC section is a complete ...
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DAC Features • 20 bit D/A Conversion • 72dB Dynamic Range, -75dB THD Stereo line-in or microphone interface with 20dB amplification • 93dB Dynamic Range, -80dB THD Stereo D/A conversion • 74dB Dynamic Range / -65dB THD for 20mW ...
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Digital Signals Timing 15.1.2.1 Data Interface To avoid noises at the output, the reset state is maintained until proper synchronism is achieved in the DAC serial interface: • DSEL • SCLK • DCLK • DOUT The data interface allows ...
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Serial Audio DAC Interface The serial audio DAC interface is a Synchronous Peripheral Interface (SPI) in slave mode: • AUDCDIN: is used to transfer data in series from the master to the slave DAC driven by the ...
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Figure 15-7. Dac SPI Interface 15.1.4 DAC Interface SPI Protocol On AUDCDIN, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a read operation. The 7 following bits are used for the register ...
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Table 15-1. Timing parameter Tc Twl Twh Tssen Thsen Tssdi Thsdi Tdsdo Thsdo 15.1.5 DAC Register Tables Table 15-2. Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Ch 0Dh 10h 11h 15.1.6 DAC Gain The DAC ...
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Table 15-3. Table 15-4. 4341H–MP3–10/07 Line-in gain LLIG 4:0 RLIG 4:0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Master Playback Gain LMPG 5:0 RMPG 5:0 000000 000001 000010 000011 ...
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Table 15-4. Table 15-5. AT8xC51SND2C/MP3B 88 Master Playback Gain (Continued) LMPG 5:0 RMPG 5:0 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Line-out Gain LLOG 5:0 ...
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Table 15-5. Table 15-6. 4341H–MP3–10/07 Line-out Gain (Continued) 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 DAC Output Level Control LOLC 2:0 ROLC ...
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Digital Mixer Control The Audio DAC features a digital mixer that allows the mixing and selection of multiple input sources. The mixing / multiplexing functions are described in the following table according with the next figure: Figure 15-9. Mixing ...
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The selection between modes is done using DINTSEL 1:0 in DAC_MISC register (refer to Table 15-22.) according to Table 15-9. Table 15-9. 15.1.9 De-emphasis and dither enable The circuit features a de-emphasis filter for the playback channel. To enable the ...
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Register Table 15-11. AUXCON Register 7 SDA Bit Number Reset Value = 1111 1111b Table 15-12. Dac Control Register Register - DAC_CTRL (00h) 7 ONPADRV Bit Number ...
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Reset Value = 00000000b Table 15-13. DAC Left Line In Gain Register - DAC_LLIG (01h Bit Number 7:5 4:0 Reset Value = 00000101b Table 15-14. DAC Right Line In Gain Register - DAC_RLIG (02h Bit ...
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Table 15-16. DAC Right Master Playback Gain Register - DAC_RMPG (04h Bit Number 7:6 5:0 Reset Value = 00001000b Table 15-17. DAC Left Line Out Gain Register - DAC_LLOG (05h Bit Number 7:6 5:0 Reset Value ...
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Table 15-19. DAC Output Level Control Register - DAC_OLC (07h) 7 RSHORT Bit Number 6:4 2:0 Reset Value = 00100010b Table 15-20. Dac Mixer Control Register - DAC_MC (08h Bit Number 7 ...
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Table 15-21. DAC Mixer Control Register - DAC_CSFC (09h Bit Number 7:5 4 3:0 Reset Value = 00000000b Table 15-22. Dac Miscellaneous Register - DAC_ MISC (0Ah Bit Number 1:0 Reset ...
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Table 15-23. DAC Precharge Control Register - DAC_ PRECH (0Ch) 7 PRCHARGE PADRV Bit Number Reset Value = 00000000b Table 15-24. DAC Auxilary input gain Register - DAC_ AUXG (0Dh ...
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Table 15-25. DAC Reset Register - DAC_ RST (10h Bit Number 7 Reset Value = 00000000b Note: 15.2 Power Amplifier High quality mono output is provided. The DAC output is connected through a buffer stage ...
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Table 15-27. PA Operating Mode APAON Table 15-28. PA Low Power Mode APALP 15.3 Audio Supplies and Start-up In operating mode AUDVBAT (supply of the audio power amplifier) must be between 3.2V and 5,5V. AUDVDD, HSVDD and VDD must be ...
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Audio DAC Start-up Sequence In order to minimize any audio output noise during the start-up, the following sequence should be applied. 15.3.1.1 Example of power-on: Path DAC to Headset Output • Desassert the Reset: write 07h at address 10h. ...
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Precharge Control The power up of the circuit can be performed independently for several blocks. The sequence flow starts by setting to High the block specific fastcharge control bit and subsequently the asso- ciated power control bit. Once the ...
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Register Table 15-30. PA Control Register - PA_CTRL (11h Bit Number 3:0 Reset Value = 00000000b AT8xC51SND2C/MP3B 102 APAON APAPRECH APALP Bit Mnemonic Description - Not used APAON Audio power ...
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... DFU functions. The Run-Time configuration co-exist with the usual functions of the device, which is USB Mass Storage for AT89C51SND2C used to initiate DFU from the nor- mal operating mode. The DFU configuration is used to perform the firmware update after device re-configuration and USB reset ...
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Figure 16-3 shows how to connect the AT8xC51SND2C to the USB connector. D+ and D- pins are connected through 2 termination resistors. A pull-up resistor is implemented inform the host of a full speed device connection. Value ...
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Serial Interface Engine (SIE) The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and unstuffing. • CRC generation and checking. • ACKs and NACKs automatic generation. • TOKEN type identifying. • Address checking. ...
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Figure 16-5. UFI Block Diagram 12 MHz DPLL Endpoint Control To/From SIE Figure 16-6. USB Typical Transaction Load OUT Transactions: HOST OUT DATA0 (n Bytes) UFI C51 IN Transactions: HOST IN UFI NACK Endpoint FIFO Write C51 AT8xC51SND2C/MP3B 106 Transfer ...
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Configuration 16.4.1 General Configuration • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (See “Clock Controller” on page 19). The USB controller should be then enabled by setting ...
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An endpoint which is not enabled won’t answer to any USB request. The Default Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard requests. • Endpoint type configuration All Standard Endpoints can be configured ...
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Read/Write Data FIFO 16.5.1 Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the data are stored into the FIFO and ...
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Bulk/Interrupt Transactions Bulk and Interrupt transactions are managed in the same way. 16.6.1 Bulk/Interrupt OUT Transactions in Standard Mode Figure 16-9. Bulk/Interrupt OUT transactions in Standard Mode An endpoint should be first enabled and configured before being able to ...
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Bulk/Interrupt OUT Transactions in Ping-pong Mode Figure 16-10. Bulk/Interrupt OUT Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on ...
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If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. 16.6.3 Bulk/Interrupt IN Transactions in Standard ...
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Bulk/Interrupt IN Transactions in Ping-pong Mode Figure 16-12. Bulk/Interrupt IN transactions in Ping-pong mode An endpoint should be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware should fill the FIFO bank 0 ...
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Control Transactions 16.7.1 Setup Stage The DIR bit in the UEPSTAX register should Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP bit in the UEPSTAX register is set by ...
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The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO Bytes have been ...
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When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with ...
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Start of Frame Detection The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the ...
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The USB controller is then re-activated. Figure 16-13. Example of a Suspend/Resume Management 16.10.3 Upstream Resume A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up purpose. When the USB controller receives the ...
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Figure 16-14. Example of REMOTE WAKEUP Management SET_FEATURE: DEVICE_REMOTE_WAKEUP Detection of a SUSPEND state upstream RESUME sent 16.11 USB Interrupt System 16.11.1 Interrupt System Priorities Figure 16-15. USB Interrupt Control System D+ USB Controller D- 4341H–MP3–10/07 USB Controller Init Set ...
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Table 16-2. 16.11.2 USB Interrupt Control System As shown in Figure 16-16, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data Host accept a In packet. • RXOUTB0: Received Out Data Bank 0 when an Out packet ...
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Figure 16-16. USB Interrupt Control Block Diagram Endpoint 0..2) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 NAKOUT UEPCONX.5 NAKIN UEPCONX.4 NAKIEN UEPCONX.6 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 ...
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Registers Table 16-3. 7 USBE Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 122 USBCON Register USBCON (S:BCh) – USB Global Control Register SUSPCLK SDRMWUP - Bit Mnemonic ...
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Table 16-4. 7 FEN Bit Number Reset Value = 0000 0000b Table 16- Bit Number Reset Value = 0000 0000b 4341H–MP3–10/07 USBADDR Register USBADDR ...
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Table 16- Bit Number Reset Value = 0001 0000b Table 16- Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 124 ...
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Table 16-8. 7 EPEN Bit Number 1-0 Reset Value = 1000 0000b 4341H–MP3–10/07 UEPCONX Register UEPCONX (S:D4h) – USB Endpoint X Control Register NAKIEN NAKOUT NAKIN Bit Mnemonic Description Endpoint Enable ...
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Table 1. UEPSTAX Register UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM 7 6 DIR RXOUTB1 STALLRQ Bit Number Bit Mnemonic Description Control Endpoint Direction Bit This bit is relevant only if ...
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Table 16- Bit Number Reset Value = 0000 0000b Table 16-10. UEPIEN Register 7 - Bit Number Reset Value = 0000 0000b 4341H–MP3–10/07 UEPRST Register UEPRST ...
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Table 16-11. UEPINT Register 7 - Bit Number Reset Value = 0000 0000b Table 16-12. UEPDATX Register 7 FDAT7 Bit Number Reset Value = XXh AT8xC51SND2C/MP3B 128 UEPINT (S:F8h Read-only) – ...
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Table 16-13. UBYCTX Register 7 - Bit Number Reset Value = 0000 0000b Table 16-14. UFNUML Register 7 FNUM7 Bit Number Reset Value = 00h 4341H–MP3–10/07 UBYCTX (S:E2h) – USB Endpoint X Byte ...
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Table 16-15. UFNUMH Register 7 - Bit Number 2-0 Reset Value = 00h Table 16-16. USBCLK Register 7 - Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 130 ...
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IDE/ATAPI Interface The AT8xC51SND2C provides an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16-bit data transfer (read or write) between the AT8xC51SND2C and the IDE device. ...
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Figure 17-2. IDE Write Waveforms Notes: 17.1.1 IDE Device Connection Figure 17-3 and Figure 17-4 show 2 examples on how to interface IDE devices to the AT8xC51SND2C. In both examples P0 carries IDE low order data bits ...
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Table 17-1. Signal Name A15:8 AD7:0 ALE RD WR 17.2 Registers Table 17-2. DAT16H (S:F9h) – Data 16 High Order Byte 7 D15 Bit Number Reset Value =XXXX XXXXb 4341H–MP3–10/07 External Data Memory Interface Signals Type Description ...
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MultiMedia Card Controller The AT8xC51SND2C implements a MultiMedia Card (MMC) controller. The MMC is used to store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or removed from the application. 18.1 Card Concept ...
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The bus communication uses a special protocol (MultiMedia Card bus protocol) which is applica- ble for all devices. Therefore, the payload data transfer between the host and the cards can be bi-directional. 18.2.1 Bus Lines The MultiMedia Card bus architecture ...
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Figure 18-1. Sequential Read Operation MCMD MDAT Figure 18-2. (Multiple) Block Read Operation MCMD Command MDAT Block Read Operation As shown in Figure 18-3 and Figure 18-4 the data write operation uses a simple busy signalling of the write operation ...
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Command Token Format As shown in Figure 18-6, commands have a fixed code length of 48 bits. Each command token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a ...
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Table 18-2. Bit Position Width (bits) Value Description Table 18-3. Bit Position Width (bits) Value Description Table 18-4. Bit Position Width (bits) Value Description Table 18-5. Bit Position Width (bits) Value Description Table 18-6. Bit Position Width (bits) Value Description ...
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Figure 18-8. Data Token Format 18.2.6 Clock Control The MMC bus clock signal can be used by the host to turn the cards into energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on ...
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Figure 18-9. MMC Controller Block Diagram OSC Generator CLOCK Internal Bus 18.4 Clock Generator The MMC clock is generated by division of the oscillator clock (F troller block as detailed in Section "Oscillator", page 13. The division factor is given ...
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Figure 18-12. Command Line Controller Block Diagram TX Pointer 5-Byte FIFO MMCMD CTPTR Write MMCON0.4 CFLCK MMSTA.0 Command Transmitter RX Pointer 17 - Byte FIFO MMCMD CRPTR Read MMCON0.5 Command Receiver 18.5.1 Command Transmitter For sending a command to the ...
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Figure 18-13. Command Transmission Flow 18.5.2 Command Receiver The end of the response reception is signalled to you by the EORI flag in MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148. ...
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Figure 18-14. Data Line Controller Block Diagram MMINT.0 MMINT.2 F1EI F1FI 8-Byte TX Pointer FIFO 1 DTPTR MMCON0.6 16-Byte FIFO MMDAT RX Pointer DRPTR 8-Byte MMCON0.7 FIFO 2 F2EI F2FI MMINT.1 MMINT.3 18.6.1 FIFO Implementation The 16-Byte FIFO is based ...
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Figure 18-15. Data Controller Configuration Flows 18.6.3 Data Transmitter 18.6.3.1 Configuration For transmitting data to the card user must first configure the data controller in transmission mode by setting the DATDIR bit in MMCON1 register. Figure 18-16 summarizes the data ...
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CBUSY toggles, i.e. when the card enters and exits its busy state. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148. Figure 18-16. Data Stream Transmission Flows Data Stream ...
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Figure 18-17. Data Block Transmission Flows Data Block Transmission FIFOs Filling write 16 data to MMDAT Start Transmission DATEN = 1 DATEN = 0 FIFO Empty? F1EI or F2EI = 1? FIFO Filling write 8 data to MMDAT No More ...
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DCR bit in MMCON2 register. This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of frame (EOFI flag ...
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Figure 18-19. Data Block Reception Flows Data Block Reception Start Transmission DATEN = 1 DATEN = 0 FIFO Full? F1EI or F2EI = 1? FIFO Reading read 8 data from MMDAT No More Data To Receive? a. Polling mode 18.6.5 ...
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The interrupt request is generated each time an unmasked flag is set, and the global MMC con- troller interrupt enable bit is set (EMMC in IEN1 register). Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This implies that ...
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Registers Table 18-8. MMCON0 (S:E4h) – MMC Control Register 0 7 DRPTR Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 150 MMCON0 Register DTPTR CRPTR CTPTR Bit Mnemonic ...
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Table 18-9. MMCON1 (S:E5h) – MMC Control Register 1 7 BLEN3 Bit Number Reset Value = 0000 0000b Table 18-10. MMCON2 Register MMCON2 (S:E6h) – MMC Control Register 2 7 MMCEN Bit Number ...
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Table 18-11. MMSTA Register MMSTA (S:DEh Read Only) – MMC Control and Status Register 7 - Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 152 CBUSY CRC16S ...
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Table 18-12. MMINT Register MMINT (S:E7h Read Only) – MMC Interrupt Register 7 MCBI Bit Number Reset Value = 0000 0011b 4341H–MP3–10/ EORI EOCI EOFI Bit Mnemonic Description MMC ...
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Table 18-13. MMMSK Register MMMSK (S:DFh) – MMC Interrupt Mask Register 7 MCBM Bit Number Reset Value = 1111 1111b Table 18-14. MMCMD Register MMCMD (S:DDh) – MMC Command Register 7 MC7 ...
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Table 18-15. MMDAT Register MMDAT (S:DCh) – MMC Data Register 7 MD7 Bit Number Reset Value = 1111 1111b Table 18-16. MMCLK Register MMCLK (S:EDh) – MMC Clock Divider Register 7 MMCD7 Bit Number ...
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Synchronous Peripheral Interface The AT8xC51SND2C implements a Synchronous Peripheral Interface with master and slave modes capability. Figure 19-1 shows an SPI bus configuration using the AT8xC51SND2C as master connected to slave peripherals while Figure 19-2 shows an SPI bus ...
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Description The SPI controller interfaces with the C51 core through three special function registers: SPCON, the SPI control register (see Table 19-2); SPSTA, the SPI status register (see Table 19-3); and SPDAT, the SPI data register (see Table 19-4). ...
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When the AT8xC51SND2C is the only slave on the bus, it can be useful not to use SS# pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no effect ...
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For simplicity, Figure 19-5 and Figure 19-6 depict the SPI waveforms in idealized form and do not provide precise timing information. For timing parameters refer to the Section “AC Characteristics”. Note: Figure 19-5. Data Transmission Format (CPHA = 0) SCK ...
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Figure 19-7. SS Timing Diagram 19.1.6 Error Conditions The following flags signal the SPI error conditions: • MODF in SPSTA signals a mode fault. MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit cleared). ...
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Slave Configuration The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been loaded is SPDAT. 19.3.3 Data Exchange There are 2 possible methods to exchange data in master and slave modes: ...
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Figure 19-9. Master SPI Polling Flows 19.3.5 Master Mode with Interrupt Figure 19-10 shows the initialization phase and the transfer phase flows using the interrupt. Using this flow prevents any overrun error occurrence. The bit rate is selected according to ...
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Figure 19-10. Master SPI Interrupt Flows 19.3.6 Slave Mode with Polling Policy Figure 19-11 shows the initialization phase and the transfer phase flows using the polling. The transfer format depends on the master controller. SPIF flag is cleared when reading ...
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Figure 19-11. Slave SPI Polling Flows 19.3.7 Slave Mode with Interrupt Policy Figure 19-10 shows the initialization phase and the transfer phase flows using the interrupt. The transfer format depends on the master controller. Reading SPSTA at the beginning of ...
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Figure 19-12. Slave SPI Interrupt Policy Flows 4341H–MP3–10/07 AT8xC51SND2C/MP3B SPI Initialization Interrupt Policy Select Slave Mode MSTR = 0 Select Format program CPOL & CPHA Enable interrupt ESPI =1 Enable SPI SPEN = 1 Prepare Transfer write data in SPDAT ...
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Registers Table 19-2. SPCON (S:C3h) – SPI Control Register 7 SPR2 Bit Number Reset Value = 0001 0100b Note: AT8xC51SND2C/MP3B 166 SPCON Register SPEN SSDIS MSTR Bit ...
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Table 19-3. SPSTA (S:C4h) – SPI Status Register 7 SPIF Bit Number Reset Value = 00000 0000b Table 19-4. SPDAT (S:C5h) – Synchronous Serial Data Register 7 SPD7 Bit Number ...
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Serial I/O Port The serial I/O port in the AT8xC51SND2C provides both synchronous and asynchronous com- munication modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode 0) and operates as an Universal Asynchronous Receiver ...
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Figure 20-1. Timer 1 Baud Rate Generator Block Diagram 20.2.2 Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer. As shown in Figure 20-2 the Internal Baud ...
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Figure 20-3. Serial I/O Port Block Diagram (Mode 0) 20.3.1 Transmission (Mode 0) To start a transmission mode 0, write to SCON register clearing bits SM0, SM1. As shown in Figure 20-4, writing the Byte to transmit to SBUF register ...
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Baud Rate Selection (Mode 0) In mode 0, the baud rate can be either, fixed or variable. As shown in Figure 20-6, the selection is done using M0SRC bit in BDRCON register. Figure 20-7 gives the baud rate calculation ...
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Figure 20-9. Data Frame Format (Mode 1) 20.4.0.2 Modes 2 and 3 Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 20-10) con- sists of 11 bits: one start bit, eight data bits (transmitted and received ...
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Baud Rate Selection (Modes 1 and 3) In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud Rate Generator and allows different baud rate in reception and transmission. As shown ...
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Table 20-2. Baud Rate 115200 57600 38400 19200 9600 4800 Baud Rate 115200 57600 38400 19200 9600 4800 Notes: 1. These frequencies are achieved in X1 mode These frequencies are achieved in X2 mode, F 20.4.5 Baud Rate ...
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Figure 20-15. Baud Rate Formula (Mode 2) 20.5 Multiprocessor Communication (Modes 2 and 3) Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable this feature, set SM2 bit in SCON register. When the multiprocessor communication ...
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SADEN = 1111 1010b Given = 1111 0X0Xb Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 0XX1b Slave C:SADDR = 1111 0011b SADEN = 1111 1101b Given = 1111 00X1b The SADEN Byte is selected so ...
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Interrupt The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 20-16 these flags are combined together to appear as ...
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Registers Table 20-3. SCON (S:98h) – Serial Control Register 7 FE/SM0 Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 178 SCON Register OVR/SM1 SM2 REN Bit Mnemonic Description ...
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Table 20-4. SBUF (S:99h) – Serial Buffer Register 7 SD7 Bit Number Reset value = XXXX XXXXb Table 20-5. SADDR (S:A9h) – Slave Individual Address Register 7 SAD7 Bit Number Reset Value = 0000 ...
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Table 20-7. BDRCON (S:92h) – Baud Rate Generator Control Register 7 - Bit Number Reset Value = XXX0 0000b Table 20-8. BRL (S:91h) – Baud Rate Generator Reload Register 7 BRL7 Bit ...
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Two-wire Interface (TWI) Controller The AT8xC51SND2C implements a TWI controller supporting the four standard master and slave modes with multimaster capability. Thus, it allows connection of slave devices like LCD controller, audio DAC, etc., but also external master controlling ...
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Figure 21-2. Complete Data Transfer on TWI Bus SDA MSB Slave Address SCL 1 S The four operating modes are: • Master transmitter • Master receiver • Slave transmitter • Slave receiver Data transfer in each mode of operation are ...
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Table 21-1. SSCRx Note: 21.1.2 Master Transmitter Mode In the master transmitter mode, a number of data Bytes are transmitted to a ...
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When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag is set again and a number of status code in SSSTA are possible. There are 40h, 48h or ...
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If the SSAA bit is reset during a transfer, the controller will transmit the last Byte of the transfer and enter state C0h or C8h. The controller is switched to the not addressed slave mode and will ignore the master ...
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Figure 21-3. Format and States in the Master Transmitter Mode Successful transmis- S sion to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data ...
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Figure 21-4. Format and States in the Master Receiver Mode Successful reception S from a slave transmitter 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data ...
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Figure 21-5. Format and States in the Slave Receiver Mode Reception of the own slave address and one or more data Bytes. All are acknowledged Last data Byte received is not acknowledged Arbitration lost as master and addressed as slave ...
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Figure 21-6. Format and States in the Slave Transmitter Mode Reception of the own slave address and transmission of one or more data Bytes. Arbitration lost as master and addressed as slave Last data Byte transmitted. Switched to not addressed ...
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Table 21-2. Status for Master Transmitter Mode Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT A START condition has 08h Write SLA+W been transmitted Write SLA+W A repeated START 10h condition has been transmitted Write ...
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Table 21-3. Status for Master Receiver Mode Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT A START condition has 08h Write SLA+R been transmitted Write SLA+R A repeated START 10h condition has been transmitted Write ...
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Table 21-4. Status for Slave Receiver Mode with Own Slave Address Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT No SSDAT action Own SLA+W has been 60h received; ACK has been returned No SSDAT action ...
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Table 21-5. Status for Slave Receiver Mode with General Call Address Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT General call address No SSDAT action has been received; 70h ACK has been No SSDAT action ...
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Table 21-6. Status for Slave Transmitter Mode Status of the TWI Bus Status and TWI Hardware Code SSSTA To/From SSDAT Write data Byte Own SLA+R has been A8h received; ACK has been returned Write data Byte Arbitration lost in Write ...
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Registers Table 21-8. 7 SDA Bit Number 7 6 5:1 0 Reset Value = 1111 1111b 4341H–MP3–10/07 AUXCON Register AUXCON (S:90h) – Auxiliary Control Register SCL - AUDCDOUT Bit Mnemonic Description TWI Serial Data SDA SDA ...
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Table 21-9. 7 SSCR2 Bit Number Reset Value = 0000 0000b AT8xC51SND2C/MP3B 196 SSCON Register SSCON (S:93h) – Synchronous Serial Control Register SSPE SSSTA SSSTO Bit Mnemonic Description Synchronous ...
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Table 21-10. SSSTA Register SSSTA (S:94h) – Synchronous Serial Status Register 7 SSC4 Bit Number 7:3 2:0 Reset Value = F8h Table 21-11. SSDAT Register SSDAT (S:95h) – Synchronous Serial Data Register 7 SSD7 Bit Number 7:1 0 Reset Value ...
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AT8xC51SND2C/MP3B 198 4341H–MP3–10/07 ...
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Analog to Digital Converter The AT8XSND2CMP3B implement a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). First channel of this ADC can be used for battery monitoring while the second one can be used for voice sampling ...
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Figure 22-2. Timing Diagram 22.1.1 Clock Generator The ADC clock is generated by division of the peripheral clock (see details in section “X2 Fea- ture”, page 14). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure ...