AT89C51CC03C-RLRIM Atmel, AT89C51CC03C-RLRIM Datasheet - Page 63
AT89C51CC03C-RLRIM
Manufacturer Part Number
AT89C51CC03C-RLRIM
Description
IC 8051 MCU FLASH 64K 44VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-RLRIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CRLRTR
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Figure 31. Serial I/O Port Block Diagram
Figure 32. Framing Error Block Diagram
4182E–CAN–05/04
Serial I/O Port
Framing Error Detection
TXD
RXD
The AT89C51CC03 I/O serial port is compatible with the I/O serial port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
•
•
Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register bit is set.
The software may examine the FE bit after each reception to check for data errors.
Once set, only software or a reset clears the FE bit. Subsequently received frames with
valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the
stop bit instead of the last data bit (See Figure 33. and Figure 34.).
SM0/FE
SMOD
Framing error detection
Automatic address recognition
Transmitter
SMOD0
SBUF
SM1
SM2
-
Mode 0 Transmit
Write SBUF
IB Bus
SCON reg
RI
REN
Set FE bit if stop bit is 0 (framing error)
SM0 to UART mode control
To UART framing error control
POF
TI
TB8
GF1
RB8
GF0
Shift register
Receive
Receiver
SBUF
PD
TI
IDL
RI
Load SBUF
Read SBUF
Serial Port
Interrupt
AT89C51CC03
Request
63
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