ATMEGA88-20PI Atmel, ATMEGA88-20PI Datasheet - Page 208
ATMEGA88-20PI
Manufacturer Part Number
ATMEGA88-20PI
Description
IC MCU AVR 8K 5V 20MHZ 28-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88-20PI
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA88-24PI
ATMEGA88-24PI
ATMEGA88-24PI
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21. 2-wire Serial Interface
21.1
21.2
21.2.1
208
Features
2-wire Serial Interface Bus Definition
ATmega48/88/168
TWI Terminology
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The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 21-1. TWI Bus Interconnection
The following definitions are frequently encountered in this section.
Table 21-1.
Term
Master
Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400 kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up When AVR is in Sleep Mode
Compatible with Philips I
SDA
SCL
TWI Terminology
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
Device 1
2
C protocol
Device 2
Device 3
........
Device n
V
CC
R1
R2
2545S–AVR–07/10
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