ATMEGA128-16MI Atmel, ATMEGA128-16MI Datasheet - Page 201
ATMEGA128-16MI
Manufacturer Part Number
ATMEGA128-16MI
Description
IC AVR MCU 128K 16MHZ IND 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128-16MI
Manufacturer:
ATMEL
Quantity:
2 395
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2467V–AVR–02/11
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the master with the shortest high period. The low period of the combined clock is equal to
the low period of the master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.
Figure 92. SCL Synchronization between Multiple Masters
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the master had output, it has
lost the arbitration. Note that a master can only lose arbitration when it outputs a high SDA value
while another master outputs a low value. The losing master should immediately go to slave
mode, checking if it is being addressed by the winning master. The SDA line should be left high,
but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one master remains, and this may take many
bits. If several masters are trying to address the same slave, arbitration will continue into the
data packet.
Figure 93. Arbitration Between two Masters
Synchronized
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
SCL from
SCL from
master A
master B
SCL Bus
Line
START
TA
Counting Low Period
low
Masters Start
TB
low
TA
Arbitration, SDA
Counting High Period
high
Masters Start
TB
Master A loses
high
ATmega128
A
SDA
201
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