PIC17C756A-16E/PT Microchip Technology, PIC17C756A-16E/PT Datasheet - Page 111
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PIC17C756A-16E/PT
Manufacturer Part Number
PIC17C756A-16E/PT
Description
IC MCU CMOS 16MHZ 16K EPRM64TQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-16E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC17C756A-16E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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This mode (3 Capture, 1 Period) is selected if control bit
CA1/PR3 is clear. In this mode, the Capture1 register,
consisting of high byte (PR3H/CA1H) and low byte
(PR3L/CA1L), is configured as the period control regis-
ter for TMR3. Capture1 is disabled in this mode and the
corresponding interrupt bit, CA1IF, is never set. TMR3
increments until it equals the value in the period regis-
ter and then resets to 0000h on the next timer clock.
All other Captures are active in this mode.
13.2.1.1
The CAxED1 and CAxED0 bits determine the event on
which capture will occur. The possible events are:
• Capture on every falling edge
• Capture on every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
When a capture takes place, an interrupt flag is latched
into the CAxIF bit. This interrupt can be enabled by set-
ting the corresponding mask bit CAxIE. The Peripheral
Interrupt Enable bit (PEIE) must be set and the Global
Interrupt Disable bit (GLINTD) must be cleared for the
interrupt to be acknowledged. The CAxIF interrupt flag
bit is cleared in software.
When the capture prescale select is changed, the pres-
caler is not reset and an event may be generated.
Therefore, the first capture after such a change will be
ambiguous. However, it sets the time-base for the next
capture. The prescaler is reset upon chip RESET.
The capture pin, CAPx, is a multiplexed pin. When
used as a port pin, the capture is not disabled. How-
ever, the user can simply disable the Capture interrupt
by clearing CAxIE. If the CAPx pin is used as an output
pin, the user can activate a capture by writing to the
port pin. This may be useful during development phase
to emulate a capture interrupt.
2000 Microchip Technology Inc.
Capture Operation
The input on the capture pin CAPx is synchronized
internally to internal phase clocks. This imposes certain
restrictions on the input waveform (see the Electrical
Specification section for timing).
The capture overflow status flag bit is double buffered.
The master bit is set if one captured word is already
residing in the Capture register (CAxH:CAxL) and
another “event” has occurred on the CAPx pin. The
new event will not transfer the TMR3 value to the cap-
ture register, protecting the previous unread capture
value. When the user reads both the high and the low
bytes (in any order) of the Capture register, the master
overflow bit is transferred to the slave overflow bit
(CAxOVF) and then the master bit is reset. The user
can then read TCONx to determine the value of CAx-
OVF.
The recommended sequence to read capture registers
and capture overflow flag bits is shown in Example 13-1.
PIC17C7XX
DS30289B-page 111
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