PIC16F874-04E/PT Microchip Technology, PIC16F874-04E/PT Datasheet - Page 306
![IC MCU FLASH 4KX14 EE 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16F874-04E/PT
Manufacturer Part Number
PIC16F874-04E/PT
Description
IC MCU FLASH 4KX14 EE 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F873-04SO.pdf
(218 pages)
4.PIC16F873-04SO.pdf
(5 pages)
5.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F874-04E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F87404E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F874-04E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F873-04SO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- Current page: 306 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.7.1
DS31017A-page 17-30
I
2
C Master Mode Operation
The master device generates all of the serial clock pulses and the START and STOP conditions.
A transfer is ended with a STOP condition or with a repeated START condition. Since the
repeated START condition is also the beginning of the next serial transfer, the I
released.
In Master transmitter mode serial data is output through SDA, while SCL outputs the serial clock.
The first byte transmitted contains the slave address of the receiving device, (7 bits) and the
Read/Write (R/W) bit. In this case the R/W bit will be logic '0'. Serial data is transmitted 8 bits at
a time. After each byte is transmitted, an acknowledge bit is received. START and STOP condi-
tions are output to indicate the beginning and the end of a serial transfer.
In Master receive mode the first byte transmitted contains the slave address of the transmitting
device (7 bits) and the R/W bit. In this case the R/W bit will be logic ‘1‘. Thus the first byte trans-
mitted is a 7-bit slave address followed by a '1' to indicate receive bit. Serial data is received via
SDA while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte
is received, an acknowledge bit is transmitted. START and STOP conditions indicate the begin-
ning and end of transmission.
The baud rate generator used for SPI mode operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I
tained in the lower 7 bits of the SSPADD register. The baud rate generator will automatically
begin counting on a write to the SSPBUF. Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK) the internal clock will automatically stop counting and
the SCL pin will remain in its last state.
A typical transmit sequence would go as follows:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
k)
l)
The user generates a Start Condition by setting the START enable bit, SEN
(SSPCON2<0>).
SSPIF is set. The SSP module will wait the required start time before any other operation
takes place.
The user loads the SSPBUF with the address to transmit.
Address is shifted out the SDA pin until all 8 bits are transmitted.
The SSP Module shifts in the ACK bit from the slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
The SSP module generates an interrupt at the end of the ninth clock cycle by setting the
SSPIF bit.
The user loads the SSPBUF with eight bits of data.
DATA is shifted out the SDA pin until all 8 bits are transmitted.
The SSP Module shifts in the ACK bit from the slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
The SSP module generates an interrupt at the end of the ninth clock cycle by setting the
SSPIF bit.
The user generates a STOP condition by setting the STOP enable bit, PEN
(SSPCON2<2>).
Interrupt is generated once the stop condition is complete.
Preliminary
2
C operation. The baud rate generator reload value is con-
1997 Microchip Technology Inc.
2
C bus will not be
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