PIC14000T-20/SS Microchip Technology, PIC14000T-20/SS Datasheet - Page 55
PIC14000T-20/SS
Manufacturer Part Number
PIC14000T-20/SS
Description
IC MCU OTP 4KX14 A/D 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 14r
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC14000-04SO.pdf
(153 pages)
4.PIC14000-04SO.pdf
(5 pages)
Specifications of PIC14000T-20/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
20
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Data Converters
Slope A/D
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SSOP
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
1
Operating Supply Voltage
2.7 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
14 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC14000-04SO PDF datasheet #3
- PIC14000-04SO PDF datasheet #4
- Current page: 55 of 153
- Download datasheet (767Kb)
7.5.4
PIC14000 is compliant with the SMBus specification
published by Intel. Some key points to note regarding
the bus specifications and how it pertains to the
PIC14000 hardware are listed below:
• SMBus has fixed input voltage thresholds.
FIGURE 7-18: SMHOG STATE MACHINE
1996 Microchip Technology Inc.
PIC14000 I/O buffers have programmable levels
that can be selected to be compatible with both
SMBus threshold levels via the SMBus and
SPGND bits in the MISC register.
SMBus
CONSIDERATIONS
AND ACCESS.bus
I
2
CIF = 1
SCL = 0
E/DRIVE
LOW
SCL
SCL = 1
D
Preliminary
I
I
2
2
CIF = 0
CIF = 1
A
• A mechanism to stretch the I
SMHOG = 0
been implemented to support SMBus slave
transactions. The SMHOG bit (MISC<7>) allows
hardware to automatically force and hold the I
clock line low when a data byte has been
received. This prevents the SMBus master from
overflowing the receive buffer in instances where
the microcontroller may be to busy servicing
higher priority tasks to respond to a I
interrupt. Or, if the microcontroller is in SLEEP
mode and needs time to wake-up and respond to
the I
2
C interrupt.
C
I
2
CIF = 0
B
I
2
I
2
CIF = 1
CIF = 0
PIC14000
2
C clock time has
DS40122B-page 55
2
C module
2
C
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