UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 986
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
LCD
controller/d
river
Function
LCDM: LCD
display mode
register
LCDC0: LCD
clock control
register 0
VLCD: LCD
boost level
control register
PFALL: Port
function register
SEGEN:
Segment enable
register
Details of
Function
To manipulate VLCON when using the internal voltage boosting method or capacitor
split method, follow the procedure below.
A. To stop the operation of the voltage boosting/capacitor split circuit after switching
B. To stop the operation of the voltage boosting/capacitor split circuit during display
C. To set display on from stop status of the voltage boosting/capacitor split circuit:
Bits 3, 6, and 7 must be set to 0.
Set the LCD clock (LCDCL) to no more than 512 Hz when the internal voltage boost
method has been set.
The VLCD setting is valid only when the voltage boost circuit is operating.
Bits 5 to 7 must be set to 0.
Be sure to change the VLCD value after having stopped the operation of the voltage
boost circuit (VLCON = 0).
These values above may change after device evaluation.
To use the internal voltage boosting method, specify the reference voltage by using
the VLCD register (or perform a reset to use the default value of the reference
voltage), wait for the reference voltage setup time (2 ms (min.)), and then set VLCON
to 1.
For 78K0R/LF3, bits 3 and 7 must be set to 0. For 78K0R/LG3 and 78K0R/LH3, bit 7
must be set to 0.
SEGEN can be written only once after reset release.
For 78K0R/LF3, bits 1 to 7 must be set to 0. For 78K0R/LG3, bits 2 to 7 must be set
to 0. For 78K0R/LH3, bits 5 to 7 must be set to 0.
display status from on to off:
1)
2)
3)
on status:
Setting
boosting/capacitor split circuit after setting display off.
1)
2)
3)
Set to display off status by setting LCDON = 0.
Set display on by setting LCDON = 1.
Disable outputs of all the segment buffers and common buffers by setting
SCOC = 0.
Stop the operation of the voltage boosting/capacitor split circuit by setting
V LCON = 0.
Start the operation of the voltage boosting/capacitor split circuit by setting
VLCON = 1, then wait for the voltage boosting/capacitor split wait time (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Set all the segment buffers and common buffers to non-display output
status by setting SCOC = 1.
prohibited.
Be
sure
Cautions
to
stop
APPENDIX C LIST OF CAUTIONS
the
operation
of
the
voltage
p.674
p.675
p.675
p.676
p.676
p.676
p.676
p.676
p.677
p.678
p.678
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