UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 982
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 982 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Configuration
of serial array
unit
Operation
stop mode
3-wire serial I/O
(CSI00, CSI01,
CSI10, CSI20)
communication
Function
SIRmn: Serial
flag clear trigger
register mn
SSm: Serial
channel start
register m
STm: Serial
channel stop
register m
SOEm: Serial
output enable
register m
SOm: Serial
output register
m
SOLm: Serial
output level
register m
ISC: Input
switch control
register
NFEN0: Noise
filter enable
register 0
Stopping the
operation by
units
Master
transmission
Master
transmission (in
continuous
transmission mode)
Master
reception
Master
transmission/
reception
Master
transmission/
reception (in
continuous
transmission/
reception mode)
Details of
Function
The MDmn0 bit can be rewritten even during operation.
The MDmn0 bit can be rewritten even during operation.
Be sure to clear bits 15 to 3 to “0”.
Be sure to clear bits 15 to 4 to “0”.
Be sure to clear bits 15 to 4 to “0”.
Be sure to clear bits 15 to 3 of SOE0, and bits 1 and 15 to 3 of SOE1 to “0”.
Be sure to set bits 11 and 3 of SO0, and bits 11 to 9, 3, and 1 of SO1 to “1”. And be
sure to clear bits 15 to 12 and 7 to 4 of SOm to “0”.
Be sure to clear bits 15 to 3, 1 to “0”.
Be sure to clear bits 7 to 5 to “0”.
Be sure to clear bits 7, 5, 3, and 1 to “0”.
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and,
even if the register is read, only the default value is read (except for input switch
control register (ISC), noise filter enable register (NFEN0), port input mode register
(PIM1, PIM7), port output mode register (POM1, POM7, POM8), port mode registers
(PM1, PM5, PM7, PM8), and port registers (P1, P5, P7, P8)).
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
Cautions
APPENDIX C LIST OF CAUTIONS
498, 500
p.462
p.465
p.466
p.467
p.468
p.469
p.470
p.474
pp.480,
p.485
pp.489,
492
pp.495,
p.499
p.464
484, 486
Page
(22/39)
982
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