UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 807
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 807 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
23.4 Cautions for Power-on-Clear Circuit
(V
of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
POR
Note 1
In a system where the supply voltage (V
<Action>
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Notes 1.
Remark n = 0 to 7
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software
counter that uses a timer, and then initialize the ports.
, V
PDR
2.
), the system may be repeatedly reset and released from the reset status. In this case, the time from release
If reset is generated again during this period, initialization processing <2> is not started.
A flowchart is shown on the next page.
No
Figure 23-3. Example of Software Processing After Reset Release (1/2)
Setting timer array unit
(to measure 50 ms)
50 ms has passed?
processing <1>
processing <2>
(TMIF0n = 1?)
Clearing WDT
Initialization
Initialization
Reset
Yes
Power-on-clear
DD
) fluctuates for a certain period in the vicinity of the POC detection voltage
;
; f
; Initial setting for port.
Check the reset source, etc.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
CLK
Source: f
Timer starts (TS0n = 1).
= Internal high-speed oscillation clock (4.08 MHz (MAX.)) (default)
where comparison value = 100: ≅ 50 ms
CLK
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
(4.08 MHz (MAX.))/2
Note 2
11
,
807
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