UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 583
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 583 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
15.1 Functions of Serial Interface IICA
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Serial interface
IICA
Serial interface IICA has the following three modes.
(1) Operation stop mode
(2) I
(3) Wakeup mode
Figure 15-1 shows a block diagram of serial interface IICA.
This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a serial
data bus (SDA0) line.
This mode complies with the I
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus. The
slave device automatically detects these received status and data by hardware. This function can simplify the part
of application program that controls the I
Since the SCL0 and SDA0 pins are used for open drain outputs, IICA requires pull-up resistors for the serial clock
line and the serial data bus line.
The STOP mode can be released by generating an interrupt request signal (INTIICA) when an extension code from
the master device or a local address has been received while in STOP mode. This can be set by using the WUP bit
of IICA control register 1 (IICCTL1).
2
Item
C bus mode (multimaster supported)
(
μ
PD78F150nA: n = 0 to 2)
78K0R/LF3
80 pins
CHAPTER 15 SERIAL INTERFACE IICA
−
2
C bus format and the master device can generated “start condition”, “address”,
2
C bus.
1 ch
(
μ
PD78F150nA: n = 3 to 5)
78K0R/LG3
100 pins
CHAPTER 15 SERIAL INTERFACE IICA
(
μ
PD78F150nA: n = 6 to 8)
78K0R/LH3
128 pins
583
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