UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 493
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 493 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
14.5.3 Master transmission/reception
to/from other device.
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
Remarks 1. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Master transmission/reception is that the 78K0R/Lx3 microcontrollers output a transfer clock and transmit/receive data
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
3-Wire Serial I/O
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
2. For 78K0R/LG3, CSI01 is not mounted.
Channel 0 of SAU0
SCK00, SI00, SO00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVFmn) only
7 or 8 bits
Max. f
Selectable by DAPmn bit
• DAPmn = 0: Data I/O starts at the start of the operation of the serial clock.
• DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
MSB or LSB first
CLK
CSI00
/4 [MHz], Min. f
CLK
/(2 × 2
Channel 1 of SAU0
SCK01, SI01, SO01
INTCSI01
11
× 128) [MHz]
CSI01
Note
Channel 2 of SAU0
SCK10, SI10, SO10
INTCSI10
f
CLK
CHAPTER 14 SERIAL ARRAY UNIT
: System clock frequency
CSI10
Channel 0 of SAU1
SCK20, SI20, SO20
INTCSI20
CSI20
493
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