UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 419
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 419 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
10.6 Cautions for A/D Converter
(1) Operating current in STOP mode
(2) Input range of ANI0 to ANI10, ANI15
(3) Conflicting operations
(4) Noise countermeasures
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remark 78K0R/LF3:
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of the A/D converter mode register
(ADM) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the A/D converter mode register (ADM)
to 0 at the same time.
When using normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1, LV0 = 0), clear bit 1 (VRGV) and bit 0
(VRON) of the analog reference voltage control register (ADVRC) to 0, and then shift to STOP mode.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start
operation.
Observe the rated range of the ANI0 to ANI10, ANI15 input voltage. If a voltage of AV
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by
<2> Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input channel
To maintain the 12-bit resolution, attention must be paid to noise input to the AV
ANI15.
<1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
<2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise,
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of conversion.
instruction upon the end of conversion
ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR or
ADCRH.
specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion
ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end
interrupt signal (INTAD) generated.
connecting external C as shown in Figure 10-26 is recommended.
78K0R/LG3, 78K0R/LH3:
ANI0-ANI6, ANI15
ANI0-ANI10, ANI15
CHAPTER 10 A/D CONVERTER
REFP
DD0
pin and pins ANI0 to ANI10,
or higher and AV
SS
or lower
419
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