UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1003

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
D.2 Revision History of Preceding Editions
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
2nd Edition
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
Edition
Modification of regulator output voltage of normal power mode
Addition of timer array unit 1
Modification of related documents
Addition of 1.1 Features
Modification of 1.3.3 78K0R/LH3
Modification of 1.4.1 78K0R/LF3, 1.4.2 78K0R/LG3, and 1.4.3 78K0R/LH3
Modification of 1.5 Outline of Functions
Modification of 2.1.3 78K0R/LH3
Addition of 2.2 Description of Pin Functions
Modification of 2.3 Pin I/O Circuits and Recommended Connection of Unused
Pins
Modification of Table 3-3 Vector Table
Modification of 3.2.4 Special function registers (SFRs)
Modification of 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers)
Modification of Table 4-4 Port functions (78K0R/LH3)
Modification of 4.2 Port Configuration
Addition of (7) Port function register (PFALL) and (8) Input switch control
register (ISC) to 4.3 Registers Controlling Port Function
Addition of 4.5 Settings of Port Mode Register and Output Latch When Using
Alternate Function
Modification of Figure 5-1 Block Diagram of Clock Generator
Modification of Figure 5-2 Format of Clock Operation Mode Control Register
(CMC)
Addition of Note 2 and Modification of Caution 1 in Figure 5-6. Format of System
Clock Control Register (CKC)
Modification of Table 5-3 Relationship Between CPU Clock and Minimum
Instruction Execution Time
Modification of Figure 5-7 Format of Peripheral Enable Register 0 (PER0)
Modification of Figure 5-8 Format of Operation Speed Mode Control Register
(OSMC)
Modification of Caution 1 in Figure 5-9 Example of External Circuit of X1
Oscillator and Figure 5-10 Example of External Circuit of XT1 Oscillator
(Crystal Oscillation)
Modification of Figure 5-12 Clock Generator Operation When Power Supply
Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option
Byte: LVIOFF = 1)) and Figure 5-13 Clock Generator Operation When Power
Supply Voltage Is Turned On (When LVI Default Start Function Enabled Is Set
(Option Byte: LVIOFF = 0))
Modification of 5.6.1 Example of controlling high-speed system clock, 5.6.2
Example of controlling internal high-speed oscillation clock, and 5.6.3 Example
of controlling subsystem clock
Description
APPENDIX D REVISION HISTORY
Throughout
INTRODUCTION
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
Chapter
(1/11)
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