UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 702
UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(7) IIC division clock select registers 0, 1 (OCKS0, OCKS1)
(8) IIC shift registers 0 to 2 (IIC0 to IIC2)
The OCKSm register controls the I
These registers control the I
via the OCKS1 register.
These registers can be read or written in 8-bit units.
Reset sets these registers to 00H.
The IICn register is used for serial transmission/reception (shift operations) synchronized with the serial clock.
These registers can be read or written in 8-bit units, but data should not be written to the IICn register during a
data transfer.
Access (read/write) the IICn register only during the wait period. Accessing this register in communication
states other than the wait period is prohibited. However, for the master device, the IICn register can be written
once only after the transmission trigger bit (IICCn.STTn bit) has been set to 1.
A wait state is released by writing the IICn register during the wait period, and data transfer is started (n = 0 to 2).
Reset sets these registers to 00H.
After reset: 00H
(n = 0 to 2)
IICn
OCKSm
(m = 0, 1)
After reset: 00H
7
OCKSTHm
OCKSENm
0
0
0
0
1
0
1
0
R/W
Other than above
R/W
2
Disable I
Enable I
OCKSm1
C00 division clock via the OCKS0 register and the I
6
0
0
0
1
1
0
2
C0n division clock (n = 0 to 2, m = 0, 1).
2
Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H
2
C division clock operation
C division clock operation
OCKSm0
User’s Manual U18953EJ5V0UD
5
Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H, IIC2 FFFFFDA0H
CHAPTER 19 I
0
0
1
0
1
0
Operation setting of I
OCKSENm OCKSTHm
f
f
f
f
f
Setting prohibited
XX
XX
XX
XX
XX
/2
/3
/4
/5
4
2
C BUS
Selection of I
3
2
C division clock
2
C division clock
0
2
OCKSm1 OCKSm0
2
C01 and I
1
2
C02 division clocks
0
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