UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 578
UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
UPD70F3737GF-GAS-AX
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16.6.9 SBF reception
UAnCTL0.UAnRXE bit to 1.
bit detection is performed.
baud rate.
complete interrupt request signal (INTUAnR) is output. The UAnOPT0.UAnSRF bit is automatically cleared and SBF
reception ends. Error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed
and UART communication error detection processing is not performed. Moreover, data transfer of the UARTAn
reception shift register and UAnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10
or fewer bits, reception is terminated as an error, an interrupt is not generated, and the SBF reception mode is
restored. The UAnSRF bit is not cleared at this time.
576
The reception enabled status is entered by setting the UAnCTL0.UAnPWR bit to 1 and then setting the
The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start
Following detection of the start bit, reception is started and the internal counter increments according to the set
When a stop bit is received, if the SBF width is 11 or more bits, it is judged as normal processing and a reception
Cautions 1. If SBF is transmitted during data reception, a framing error occurs.
(a) Normal SBF reception (detection of stop bit after more than 10.5 bits)
(b) SBF reception error (detection of stop bit after 10.5 or fewer bits)
2. Do not set the SBF reception trigger bit (UAnSRT) and SBF transmission trigger bit (UAnSTT)
INTUAnR
interrupt
RXDAn
UAnSRF
to 1 during SBF reception (UAnSRF = 1).
RXDAn
UAnSRF
INTUAnR
interrupt
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
1
1
2
Figure 16-14. SBF Reception
2
User’s Manual U18953EJ5V0UD
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3
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4
5
5
6
11.5
10.5
6
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