UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 357
UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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TQ0IOC0
TQ0IOC2
(c) TMQ0 I/O control register 0 (TQ0IOC0)
(d) TMQ0 I/O control register 2 (TQ0IOC2)
(e) TMQ0 counter read buffer register (TQ0CNT)
(f) TMQ0 capture/compare register 0 (TQ0CCR0)
Note The TQ0EES1 and TQ0EES0 bits can only be set to 1 when the timer output (TOQ01 to TOQ03)
The value of the 16-bit counter can be read by reading this register.
I
Interval = (D
f the TQ0CCR0 register is set to D
TQ0OL3
0/1
0
is used. Note that when setting these bits to 1, the TQ0CCR0 to TQ0CCR3 registers must be
set to the same value (that is, the same value as the value already specified for these registers).
TQ0OE3 TQ0OL2 TQ0OE2
0
0/1
+ 1) × Count clock cycle
0
Figure 8-8. Register Settings in Interval Timer Mode (2/3)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0/1
0
0/1
User’s Manual U18953EJ5V0UD
0
0
, the interval is as follows:
TQ0OL1
TQ0EES1
0/1
0/1
Note
TQ0OE1 TQ0OL0 TQ0OE0
TQ0EES0 TQ0ETS1 TQ0ETS0
0/1
0/1
Note
0/1
0
0/1
0
0: Disable TOQ00 pin output.
1: Enable TOQ00 pin output.
Output level when TOQ00 pin
is disabled:
0: Low level
1: High level
0: Disable TOQ01 pin output.
1: Enable TOQ01 pin output.
Output level when TOQ01 pin
is disabled:
0: Low level
1: High level
0: Disable TOQ02 pin output.
1: Enable TOQ02 pin output.
0: Disable TOQ03 pin output.
1: Enable TOQ03 pin output.
Output level when TOQ03 pin
is disabled:
0: Low level
1: High level
Output level when TOQ02 pin
is disabled:
0: Low level
1: High level
These bits select the valid
edge of the external event
count input (TIQ00 pin).
355
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