M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 126
M30835FJGP#U3
Manufacturer Part Number
M30835FJGP#U3
Description
IC M32C/83 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30835FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table 10.5 Interrupts without Interrupt Priority Levels and IPL
Table 10.4 Interrupt Sequence Execution Time
2
0
NOTES:
Watchdog Timer, NMI, Oscillation Stop Detect
Reset
Software, Address Match
_______
Peripheral Function
INT Instruction
NMI
Watchdog Timer
Undefined Instruction
Address Match
Overflow
BRK Instruction (relocatable vector table)
BRK Instruction (fixed vector table)
High-Speed Interrupt
10.6.5 IPL Change when Interrupt Request is Acknowledged
1
C
9
3 .
B
1. Allocate interrupt vectors to even addresses.
2. Vectors are fixed to even addresses.
When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowl-
edged interrupt.
Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has
no interrupt priority level is acknowledged, the value shown in Table 10.5 is set in IPL as the interrupt
priority level.
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
3 .
1
u
, 1
3
p
1
2
(
M
0
0
Interrupt
3
_______
Interrupt Sources
6
2
C
8 /
Page 101
, 3
M
3
2
C
f o
8 /
4
3
8
) T
8
Even address
Odd address
Even address
Odd address
Even address
Even address
Even address
Odd address
Even address
Vector table is internal register
Interrupt Vector Address
(1)
(1)
(1)
(2)
(2)
(2)
7
0
Not changed
Level that is Set to IPL
14 cycles
16 cycles
12 cycles
14 cycles
13 cycles
14 cycles
17 cycles
19 cycles
19 cycles
5 cycles
16-Bit Bus
16 cycles
16 cycles
14 cycles
14 cycles
15 cycles
16 cycles
19 cycles
19 cycles
21 cycles
8-Bit Bus
10. Interrupts
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