M30620FCAFP#U3 Renesas Electronics America, M30620FCAFP#U3 Datasheet - Page 552
M30620FCAFP#U3
Manufacturer Part Number
M30620FCAFP#U3
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.M30622SAFPU5.pdf
(277 pages)
2.M30622SAFPU5.pdf
(617 pages)
3.M30622SAFPU5.pdf
(308 pages)
Specifications of M30620FCAFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCAFP#U3M30620FCAFP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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External Buses
(4) Output enable time [ta(OE)]
(5) Data setup time [tsu(D)]
(b) Vcc = 3V
• With the Wait option cleared
• With the Wait option selected
Output enable time [ta(OE)] must satisfy the following conditional expressions:
(a) Vcc = 5V
• With the Wait option cleared
• With the Wait option selected
(b) Vcc = 3V
• With the Wait option cleared
• With the Wait option selected
Data setup time [tsu(D)] must satisfy the following conditional expressions:
(a) Vcc = 5V
• With the Wait option cleared
• With the Wait option selected
(b) Vcc = 3V
• With the Wait option cleared
• With the Wait option selected
ta(S) < 10
ta(S) < 2 X10
ta(OE) < 10
ta(OE) < 3 X 10
ta(OE) < 10
ta(OE) < 3X10
tsu(D) < 10
tsu(D) < 10
tsu(D) < 10
tsu(D) < 10
* 140(ns) = td(BCLK – CS) + tsu(DB – RD) – th(BCLK – RD)
* 40(ns)
* 80(ns)
9
/f(BCLK) – 140(ns)*
9
9
9
9
9
9
/(f(BCLK) X 2) – 40(ns)*
/f(BCLK) – 40(ns)*
/(f(BCLK) X 2) – 80(ns)*
/f(BCLK) – 80(ns)*
= (chip select output delay time) + (data input setup time) – (RD signal output hold time)
/(f(BCLK) X 2) – 45(ns) = tac1(RD-DB)
/(f(BCLK) X 2) – 90(ns) = tac1(RD-DB)
= td(BCLK – DB) – th(BCLK – WR)
= (data output delay time) – (WR signal output hold time)
= td(BCLK – DB) – th(BCLK – WR)
= (data output delay time) – (WR signal output hold time)
9
/f(BCLK) – 140(ns)*
9
/(f(BCLK) X 2) – 90(ns) = tac2(RD-DB)
9
/(f(BCLK) X 2) – 45(ns) = tac2(RD-DB)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C / 62A Group
Mitsubishi microcomputers
2-233
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