DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 504
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection,
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation
when there is no valid transmit data in TDR in MSB data transmission.
Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or
disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin
functions as an I/O port, the serial clock output pin, or the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The
CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note
that the SCI’s operating mode must be decided using SMR before setting the CKE1 and CKE0 bits.
Rev.6.00 Oct.28.2004 page 474 of 1016
REJ09B0138-0600H
and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is
received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
TEND flag to 0, or clearing the TEIE bit to 0.
Bit 3
MPIE
0
1
Bit 2
TEIE
0
1
Description
Multiprocessor interrupts disabled (normal reception performed)
[Clearing conditions]
Multiprocessor interrupts enabled*
Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and
setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Description
Transmit end interrupt (TEI) request disabled*
Transmit end interrupt (TEI) request enabled*
When the MPIE bit is cleared to 0
When MPB= 1 data is received
(Initial value)
(Initial value)
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