DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 390
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 390 of 1049
- Download datasheet (5Mb)
Rev.6.00 Oct.28.2004 page 360 of 1016
REJ09B0138-0600H
Channel
4
Channel
5
Bit 3
IOA3
0
1
Bit 3
IOA3
0
1
Bit 2
IOA2
0
1
0
1
Bit 2
IOA2
0
1
Bit 1
IOA1
0
1
0
1
0
1
Bit 1
IOA1
0
1
0
1
0
1
Bit 0
IOA0 Description
0
1
0
1
0
1
0
1
0
1
Bit 0
IOA0 Description
0
1
0
1
0
1
0
1
0
1
TGR4A is Output disabled
output
compare
register
TGR4A is
input
capture
register
TGR5A is Output disabled
output
compare
register
TGR5A is
input
capture
register
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCA4 pin
Capture input
source is TGR3A
compare match/
input capture
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCA5 pin
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR3A compare match/input
capture
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
(Initial value)
(Initial value)
: Don’t care
: Don’t care
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