DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 245
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.5.8
DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that
can be specified depend on the transfer mode and the channel, as shown in table 7-12.
Table 7-12 DMAC Activation Sources
Legend:
Activation by Internal Interrupt: An interrupt request selected as a DMAC activation source can be sent simultaneously
to the CPU and DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller.
Consequently, interrupt controller priority settings are not accepted.
If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source
(DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts,
however, the interrupt source flag is not cleared unless the prescribed register is accessed in a DMA transfer. If the same
interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highest-
priority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is
carried out in order of priority.
When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the
DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC.
In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not
cleared by the DMAC.
: Can be specified
: Cannot be specified
DMAC Activation Sources
Activation Source
Internal
Interrupts
External
Requests
Auto-request
ADI
TXI0
RXI0
TXI1
RXI1
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
DREQ pin falling edge input
DREQ pin low-level input
Channels
0A and 1A
Short Address Mode
Channels
0B and 1B
Rev.6.00 Oct.28.2004 page 215 of 1016
Normal
Mode
Full Address Mode
Block
Transfer
Mode
REJ09B0138-0600H
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