R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 623

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
Revision History
Date
94, 97, 98
101-103
145-148
93, 94
Page
105
107
109
112
113
116
134
137
138
146
158
71
93
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Chapter 5. Resets
Chapter 6. Power Management
Chapter 7. Processor Mode
Chapter 8. Clock
Chapter 9. Bus
Chapter 10. Protection
Chapter 11. Interrupts
• Corrected a typo “pultiple” in line 2 of 5.4 , to “multiple”
• Made minor text modifications to this chapter
• Made minor text modification to this chapter
• Made minor text modifications to this chapter
• Added “in the PLC1 register” to “SEO bit” in Figure 8.13
• Added description to Note 1 for registers PLC0 and PLC1 in
• Deleted description associated with frequency from line 14 below
• Added description for the following bits: BCS, CM04, CM05, CM10,
• Added description for procedure (6) to 8.7.2.2
• Added I
• Moved previous Table 8.7 with one sentence above the table to
• Added I
• Made minor text modifications to this chapter
• Deleted description for frequency and Note 1 in Figure 9.1 ;
• Modified peripheral bus width in line 1 of 9.2 , from “16-bit width” to
• Deleted description for 00b of PRD4 to PRD0 and PWR4 to PWR0
• Modified description for setting the P5_7B bit to 0 in Figure 9.5 :
• Deleted “(i = 0 to 3)” from Figure 9.17
• Made minor text modifications to this chapter
• Added “I2CMR” as a protected register for PRC1 bit, to Table 10.1
• Deleted “(i = 0 to 7)” from the title of Table 10.2
• Made minor text modifications to this chapter
• Added details to “Reference” in Tables 11.2 to 11.5
• Changed expression “Multi-master I
• Modified “Bits RLVL02 to RLVL00” and “Bits RLVL12 to RLVL10” in
Figures 8.14 and 8.15 , respectively
Figure 8.15 , line 2 of 8.3 , and line 2 of 8.4
CM20, CM30, and CM31, to Figures 8.17 to 8.19
8.6
8.7.3.3 as Table 8.8
Modified description for peripheral data bus “16-bit”, to “16-/32-bit”
“16-/32-bit width”
in Figure 9.2
“Output RDY from P5_7”, to “ RDY input pin”
and Figure 10.1 ; Changed the order of registers for PRC1 and
PRC2
Table 11.3 to “I
Figure 11.8 , to “Bits RLVL2 to RLVL0 in the RIPL1 register” and
“Bits RLVL2 to RLVL0 in the RIPL2 register”, respectively
R32C/117 Group User’s Manual: Hardware
2
2
C-bus interface interrupt and I
C-bus line interrupt to Table 8.8
B- 2
2
C-bus interface”
Description
Summary
2
C-bus interface” in Note 3 of
2
C-bus line interrupt to Table