R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 415

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
24.4
Figure 24.19 Example Operation of the START Condition Redundancy Prevention Function
Figure 24.20 Enabled Duration of the START Condition Redundancy Prevention Function
A START condition is generated when the bus is free (confirmed with the BBSY bit in the I2CSR register).
However, before a START condition is generated, if a different master device generates another START
condition, the BBSY bit may become 1. In this case, the START condition redundancy prevention function
terminates the generation of its own START condition.
The START condition redundancy prevention functions as follows:
Figure 24.19 shows the operation of the START condition redundancy prevention function.
The START condition redundancy prevention function is enabled from the falling edge of an SDA line in a
START condition until the slave address is completely received. This means, when registers I2CSR and
I2CTRSR are written during this period, then the START condition redundancy prevention function is
enabled. Figure 24.20 shows the duration.
BBSY bit in the
BBSY bit in the
Example behavior of when a START condition from another device is generated while in a START condition standby state.
I2CSR register
I2CSR register
I2CSR register
I2CSR register
MST bit in the
I2CSR regiter
TRS bit in the
• The START condition standby setting is disabled (exits from standby state)
• Writing to the I2CTRSR register is disabled (generation of the START condition trigger is disabled)
• Bits MST and TRS in the I2CSR register become 0 (enters into slave-receive mode)
• The AL bit in the I2CSR register becomes 1 (arbitration lost is detected)
AL bit in the
MSDA pin
MSCL pin
START Condition Redundancy Prevention Function
MSDA
MSCL
Rev.1.10
1
Bus is free
2
1st bit
3
1st clock
Valid duration of START condition redundancy prevention function
4
2nd bit
5
2nd clock
1.5 cycles of φIIC
Bus is busy
1. Confirm the bus is free
2. START condition standby setting
3. Another START condition generated by external
4. START condition detected
5. Enter slave-receive mode
device
The bus becomes busy at the same time the
START condition redundancy prevention function
is enabled (arbitration lost is generated).
24. Multi-master I
8th bit
8th clock
ACK bit
ACK clock
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C-bus Interface