R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 378

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
Figure 23.27 SR Waveform Output Mode Operation (i = 0 to 2)
Case 1: Free-running operation (Bits RST2 to RST0 in the GiBCR1 register are set to 000b)
Case 2: The base timer is reset by matching the base timer value with the GiPO0 register setting
Notes:
This figure above applies under the following conditions:
- Bits UD1 and UD0 in the GiBCR1 register are set to 00b (increment counting mode)
- m < n
This figure above applies under the following conditions:
- The IVL bit is set to 0 (low level is output as default value) and the INV bit is set to 0 (output is not inverted).
- Bits UD1 and UD0 in the GiBCR1 register are set to 00b (increment counting mode)
- m < n < p + 2
Base timer i
Input to the IIOi_j
pin
Input to the IIOi_j
pin
POijR bit
POikR bit
j = 0, 2, 4, 6; k = j + 1
m: GiPOj register setting value, 0000h to FFFFh
n: GiPOk register setting value, 0000h to FFFFh
POijR bit, POikR bit: Bits in registers IIO0IR to IIO11IR
Base timer i
Input to the IIOi_j
pin
POijR bit
POikR bit
j = 2, 4, 6; k = j + 1
m: GiPOj register setting value, 0000h to FFFFh
n: GiPOk register setting value, 0000h to FFFDh
p: GiPO0 register setting value, 0001h to FFFDh
POijR bit, POikR bit: Bits in registers IIO0IR to IIO11IR
(1)
(2)
1. Output waveform when the INV bit in the GiPOCRj register is set to 0 (output is not inverted) and the IVL bit is set to 0 (low
2. Output waveform when the INV bit is set to 0 (output is not inverted) and the IVL bit is set to 1 (high level is output as
(Bits RST2 to RST0 in the GiBCR1 register are set to 010b)
level is output as default value).
default value).
Rev.1.10
FFFFh
0000h
0000h
m
m
n
p
n
n - m
n - m
fBTi
fBTi
p + 2
fBTi
A 0 should be
written by a
program, if required
65536
A 0 should be
written by a
program, if required
fBTi
65536 - n + m
p + 2 - n + m
fBTi
fBTi
A 0 should be
written by a
program, if required
A 0 should be
written by a
program, if required
23. Intelligent I/O
Page 361 of 604