R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 173

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
11.6.5
Figure 11.6
Table 11.7
Notes:
Peripheral
INT instruction
NMI
Watchdog timer
Oscillator stop detection
Low voltage detection
Undefined instruction
Overflow
BRK instruction (relocatable vector table)
BRK instruction (fixed vector table)
BRK2 instruction
Fast interrupt
1.
2.
Interrupt request
is generated
The interrupt response time, as shown in Figure 11.6, consists of two non-overlapping time segments:
(a) the period from when an interrupt request is generated until the instruction being executed is
completed; and (b) the period required for the interrupt sequence.
Period (a) varies depending on the instruction being executed. Instructions, such as LDCTX and
STCTX in which registers are sequentially saved/restored into/from the stack, require the longest time.
For example, the STCTX instruction requires at least 30 cycles for ten registers to be saved. It requires
more time if the WAIT instruction is in the stack.
Period (b) is listed in Table 11.7.
The interrupt vectors should be aligned in addresses in multiples of 4 of internal ROM. The fast
interrupt is independent of this condition.
α is the number of waits to access SFR minus 2.
Interrupt Response Time
Interrupt Sequence Execution Time
Interrupt Response Time
(a) Period from when an interrupt request is generated until when the instruction
(b) Period required to perform an interrupt sequence
Interrupt
Rev.1.10
being executed has been completed
Instruction
(a)
Interrupt response time
Interrupt request
is accepted
Interrupt sequence
Execution Time in Terms of CPU Clock
(b)
(1)
13 + α cycles
10 cycles
12 cycles
12 cycles
16 cycles
19 cycles
19 cycles
11 cycles
11 cycles
11 cycles
an interrupt handler
(2)
Instruction in
Time
Page 156 of 604
11. Interrupts