R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 15

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26. I/O Pins
25.2
25.3
25.4
25.5
25.6
25.7
26.1
26.2
25.1.6
25.1.7
25.1.8
25.1.9
25.1.10
25.1.11
25.1.12
25.1.13
25.1.14
25.1.15
25.1.16
25.1.17
25.1.18
25.1.19
25.1.20
25.1.21
25.1.22
25.1.23
25.1.24
25.1.25
25.2.1
25.2.2
25.2.3
25.2.4
25.2.5
25.3.1
25.3.2
25.3.3
25.6.1
25.6.2
Operating Mode ........................................................................................................................... 458
CAN Communication Speed Configuration.................................................................................. 464
Mailbox and Mask Register Structure .......................................................................................... 466
Acceptance Filtering and Masking Function ................................................................................ 468
Reception and Transmission ....................................................................................................... 471
CAN Interrupt............................................................................................................................... 475
Port Pi Direction Register (PDi Register, i = 0 to 15) ................................................................... 477
Output Function Select Register.................................................................................................. 478
CAN0 Status Register (C0STR Register) ............................................................................ 437
CAN Reset Mode.................................................................................................................. 459
CAN Halt Mode..................................................................................................................... 460
CAN Sleep Mode.................................................................................................................. 461
CAN Operation Mode (Bus-Off State)................................................................................... 463
CAN Clock Configuration...................................................................................................... 464
Bit Timing Configuration ....................................................................................................... 464
Bit rate .................................................................................................................................. 465
Reception ............................................................................................................................. 472
Transmission ........................................................................................................................ 474
(n = 0, 1) ............................................................................................................................... 419
CAN0 Mask Invalid Register (C0MKIVLR Register) ............................................................ 421
CAN0 Mailbox (C0MBj Register) (j = 0 to 31)....................................................................... 422
CAN0 Mailbox Interrupt Enable Register (C0MIER Register) ............................................. 426
CAN0 Message Control Register j (C0MCTLj Register) (j = 0 to 31) ................................... 427
CAN0 Receive FIFO Control Register (C0RFCR Register) ................................................ 430
CAN0 Receive FIFO Pointer Control Register (C0RFPCR Register) .................................. 433
CAN0 Transmit FIFO Control Register (C0TFCR Register) ................................................ 434
CAN0 Transmit FIFO Pointer Control Register (C0TFPCR Register) ................................. 436
CAN0 Mailbox Search Mode Register (C0MSMR Register) ............................................... 440
CAN0 Mailbox Search Status Register (C0MSSR Register) ............................................... 441
CAN0 Channel Search Support Register (C0CSSR Register) ............................................ 443
CAN0 Acceptance Filter Support Register (C0AFSR Register) .......................................... 444
CAN0 Error Interrupt Enable Register (C0EIER Register) .................................................. 445
CAN0 Error Interrupt Factor Judge Register (C0EIFR Register) ......................................... 447
CAN0 Receive Error Count Register (C0RECR Register) .................................................. 450
CAN0 Transmit Error Count Register (C0TECR Register) .................................................. 451
CAN0 Error Code Store Register (C0ECSR Register) ........................................................ 452
CAN0 Time Stamp Register (C0TSR Register) ................................................................... 454
CAN0 Test Control Register (C0TCR Register) ................................................................... 455
CAN Operation Mode (Excluding Bus-Off State) .................................................................. 462
A- 8
476