HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 597
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bit
5
4
3
Bit Name Initial Value Slave Host Description
SDWN
ABRT
IBFIE3
0
0
0
R/(W) * —
R/W
R/(W) * —
R/W
—
LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware shutdown request is
generated.
0: [Clearing conditions]
1: [Setting condition]
LPCPD pin falling edge detection
LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle
IDR3 and TWR Receive Completion Interrupt
Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
1: [When TWRIE = 0 in LADR3]
completed interrupt requests disabled
Writing 0 after reading SDWN = 1
LPC hardware reset and LPC software reset
Writing 0 after reading ABRT = 1
LPC hardware reset and LPC software reset
LPC hardware shutdown and LPC software
shutdown
Input data register (IDR3) receive completed
interrupt requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive
completed interrupt requests enabled
Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 541 of 788
REJ09B0300-0300
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