HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 493
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Notes: 1. Only 0 can be written, to clear the flag.
Bit Bit Name
3
2
1
0
CLR3
CLR2
CLR1
CLR0
2. This bit is always read as 1.
Initial Value R/W
1
1
1
1
W *
W *
W *
W *
2
2
2
2
Description
IIC Clear 3 to 0
Controls initialization of the internal state of IIC_0 and
IIC_1.
00--: Setting prohibited
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal latch cleared
0111: IIC_0 and IIC_1 internal latches cleared
1---: Invalid setting
When a write operation is performed on these bits, a clear
signal is generated for the internal latch circuit of the
corresponding module, and the internal state of the IIC
module is initialized.
These bits can only be written to; they are always read as
1. Write data to this bit is not retained.
To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not
use a bit manipulation instruction such as BCLR.
When clearing is required again, all the bits must be written
to in accordance with the setting.
If the function of these bits is not used, set all of the CLR3
to CLR0 bits to 1 when writing to DDCSWR.
Section 16 I
Rev. 3.00 Mar 21, 2006 page 437 of 788
2
C Bus Interface (IIC) (Optional)
REJ09B0300-0300
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