HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 461
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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15.8
Table 15.11 shows the interrupt sources in serial communication interface. A different interrupt
vector is assigned to each interrupt source, and individual interrupt sources can be enabled or
disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data
transfer by the DTC.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 15.11 SCI Interrupt Sources
Channel
0
1
2
Interrupt Sources
Name
ERI0
RXI0
TXI0
TEI0
ERI1
RXI1
TXI1
TEI1
ERI2
RXI2
TXI2
TEI2
Interrupt Source
Receive error
Receive data full
Transmit data empty
Transmit end
Receive error
Receive data full
Transmit data empty
Transmit end
Receive error
Receive data full
Transmit data empty
Transmit end
Section 15 Serial Communication Interface (SCI and IrDA)
Interrupt Flag
ORER, FER, PER
RDRF
TDRE
TEND
ORER, FER, PER
RDRF
TDRE
TEND
ORER, FER, PER
RDRF
TDRE
TEND
Rev. 3.00 Mar 21, 2006 page 405 of 788
DTC Activation
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
REJ09B0300-0300
Priority
High
Low
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