HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 393
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Table 13.8 Examples of TCR, TCSR, and TCORB Settings
Register
TCR in
TMR_1
TCSR in
TMR_1
TCORB in TMR_1
IHI signal
IVI signal (PDC signal)
IVO signal
(without fall modification,
with IHI synchronization)
IVO signal
(with fall modification
and IHI synchronization)
IVO signal
(with fall modification,
without IHI synchronization)
Figure 13.7 Fall Modification and IHI Synchronization Timing Chart
Bit
7
6
5
4 and 3
2 to 0
3 to 0
Abbreviation
CMIEB
CMIEA
OVIE
CCLR1 and
CCLR0
CKS2 to CKS0
OS3 to OS0
Contents
0
0
0
11
101
0011
1001
H'03
(example)
Description
Interrupts due to compare-match and
overflow are disabled
TCNT is cleared by the rising edge of the
external reset signal (inverse of the IVI
signal)
of the external clock (IHI signal)
Not changed by compare-match B;
output inverted by compare-match A
(toggle output)
When TCORB < TCORA, 1 output on
compare-match B, 0 output on compare-
match A
Compare-match on the 4th (example)
rise of the IHI signal after the rise of the
inverse of the IVI signal
TCNT is incremented on the rising edge
Rev. 3.00 Mar 21, 2006 page 337 of 788
TCNT
0
Section 13 Timer Connection
1
2
3
TCNT = TCORB (3)
REJ09B0300-0300
4
5
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