HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 389
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Table 13.6 Examples of TCR and TCSR Settings
Register
TCR in TMR_1
TCSR in TMR_1 3 to 0
TCR in FRT
TCSR in FRT
Bit
7
6
5
4 and 3 CCLR1 and
2 to 0
6
1 and 0 CKS1 and CKS0
0
Abbreviation
CMIEB
CMIEA
OVIE
CCLR0
CKS2 to CKS0
OS3 to OS0
IEDGB
CCLRA
Contents Description
0
0
0
11
101
0011
1001
0/1
01
0
Rev. 3.00 Mar 21, 2006 page 333 of 788
Interrupts due to compare-match and
overflow are disabled
TCNT is cleared by the rising edge of
the external reset signal (inverse of
the IVI signal)
TCNT is incremented on the rising
edge of the external clock (IHI signal)
Not changed by compare-match B;
output inverted by compare-match A
(toggle output): Division by 512
When TCORB < TCORA, 1 output
on compare-match B, and 0 output
on compare-match A: Division by
256
0: FRC value is transferred to ICRB
1: FRC value is transferred to ICRB
FRC is incremented on internal
clock: /8
FRC clearing is disabled
on falling edge of input capture
input B (IHI divided signal
waveform)
on rising edge of input capture
input B (IHI divided signal
waveform)
Section 13 Timer Connection
REJ09B0300-0300
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