HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 330
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 11 16-Bit Free-Running Timer (FRT)
11.5.4
The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is
selected.
If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock ( ). Figure 11.8 shows the timing for this case.
11.5.5
ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how
input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and
IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0),
so that input capture is performed on both the rising and falling edges of FTIA.
Rev. 3.00 Mar 21, 2006 page 274 of 788
REJ09B0300-0300
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read)
Input capture
input pin
Input capture signal
Input capture
input pin
Input capture signal
Input Capture Input Timing
Buffered Input Capture Input Timing
Figure 11.7 Input Capture Input Signal Timing (Usual Case)
Read cycle of ICRA to ICRD
T 1
T 2
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