HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 184
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 6 Bus Controller (BSC)
RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the
RAME bit is cleared to 0.
6.4.4
The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding
external address space is accessed. Figure 6.2 shows an example of IOS signal output timing.
Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In extended
mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE
bit to 1. For details, refer to section 8, I/O Ports.
The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR,
as shown in table 6.3.
Table 6.3
IOS1
0
1
Rev. 3.00 Mar 21, 2006 page 128 of 788
REJ09B0300-0300
I/O Select Signals
Address Range for IOS
IOS0
0
1
0
1
Address bus
IOS
Figure 6.2 IOS
IOS
IOS
IOS
IOS Signal Output Range
H'(FF)F000 to H'(FF)F03F
H'(FF)F000 to H'(FF)F0FF
H'(FF)F000 to H'(FF)F3FF
H'(FF)F000 to H'(FF)F7FF
IOS Signal Output
IOS
IOS
T
1
IOS
IOS
IOS Signal Output Timing
External addresses selected by IOS
Bus cycle
T
2
T
3
(Initial value)
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