R5F61622N50FPV Renesas Electronics America, R5F61622N50FPV Datasheet - Page 642

• Manufacturer Part Number: R5F61622N50FPV
• Description: MCU 24KB FLASH 256K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61622N50FPV

• Core Size: 16/32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: H8SX
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b, 6x16b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• No. Of I/o's: 74
• Ram Memory Size: 24KB
• Cpu Speed: 50MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface (SCI)
Rev. 2.00 Sep. 16, 2009 Page 612 of 1036
REJ09B0414-0200
Bit
3
2
Bit Name
MPIE
TEIE
Initial
Value
0
0
R/W
R/W
R/W
Description
Multiprocessor Interrupt Enable (valid only when the MP
bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1,
this bit is automatically cleared and normal reception is
resumed. For details, see section 16.5, Multiprocessor
Communication Function.
When receive data including MPB = 0 in SSR is being
received, transfer of the received data from RSR to
RDR, detection of reception errors, and the settings of
RDRF, FER, and ORER flags in SSR are not
performed. When receive data including MPB = 1 is
received, the MPB bit in SSR is set to 1, the MPIE bit is
automatically cleared to 0, and RXI and ERI interrupt
requests (in the case where the TIE and RIE bits in
SCR are set to 1) and setting of the FER and ORER
flags are enabled.
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled. A TEI interrupt request can be cancelled by
reading 1 from the TDRE flag and then clearing the flag
to 0 in order to clear the TEND flag to 0, or by clearing
the TEIE bit to 0.