R5F61622N50FPV Renesas Electronics America, R5F61622N50FPV Datasheet - Page 15

• Manufacturer Part Number: R5F61622N50FPV
• Description: MCU 24KB FLASH 256K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61622N50FPV

• Core Size: 16/32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: H8SX
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b, 6x16b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• No. Of I/o's: 74
• Ram Memory Size: 24KB
• Cpu Speed: 50MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.3
8.4
8.5
8.6
8.7
8.8
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
Bus Configuration............................................................................................................. 180
Multi-Clock Function and Number of Access Cycles ...................................................... 181
External Bus...................................................................................................................... 185
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
Basic Bus Interface ........................................................................................................... 202
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
Byte Control SRAM Interface .......................................................................................... 215
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
8.7.7
8.7.8
Burst ROM Interface ........................................................................................................ 223
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
Idle Control Register (IDLCR) ......................................................................... 170
Bus Control Register 1 (BCR1) ........................................................................ 172
Bus Control Register 2 (BCR2) ........................................................................ 174
Endian Control Register (ENDIANCR)............................................................ 175
SRAM Mode Control Register (SRAMCR) ..................................................... 176
Burst ROM Interface Control Register (BROMCR)......................................... 177
Address/Data Multiplexed I/O Control Register (MPXCR) ............................. 179
Input/Output Pins.............................................................................................. 185
Area Division.................................................................................................... 188
Chip Select Signals ........................................................................................... 189
External Bus Interface....................................................................................... 190
Area and External Bus Interface ....................................................................... 194
Endian and Data Alignment.............................................................................. 199
Data Bus............................................................................................................ 202
I/O Pins Used for Basic Bus Interface .............................................................. 202
Basic Timing..................................................................................................... 203
Wait Control ..................................................................................................... 209
Read Strobe (RD) Timing................................................................................. 211
Extension of Chip Select (CS) Assertion Period............................................... 212
DACK Signal Output Timing ........................................................................... 214
Byte Control SRAM Space Setting................................................................... 215
Data Bus............................................................................................................ 215
I/O Pins Used for Byte Control SRAM Interface ............................................. 216
Basic Timing..................................................................................................... 217
Wait Control ..................................................................................................... 219
Read Strobe (RD).............................................................................................. 221
Extension of Chip Select (CS) Assertion Period............................................... 221
DACK Signal Output Timing ........................................................................... 221
Burst ROM Space Setting................................................................................. 223
Data Bus............................................................................................................ 223
I/O Pins Used for Burst ROM Interface............................................................ 224
Basic Timing..................................................................................................... 225
Wait Control ..................................................................................................... 227
Read Strobe (RD) Timing................................................................................. 227
Rev. 2.00 Sep. 16, 2009 Page xiii of xxviii