M30802SGP#U5 Renesas Electronics America, M30802SGP#U5 Datasheet - Page 269

• Manufacturer Part Number: M30802SGP#U5
• Description: IC M16C MCU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802SGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 81
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Switching characteristics (referenced to V
Table 28.39 Memory expansion and microprocessor modes
1 .
0
Note 1: Calculated according to the BCLK frequency as follows:
C
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
9
t
t
0 .
h(RD-AD)
h(WR-AD)
h(RD-CS)
h(WR-CS)
d(BCLK-ALE)
h(BCLK-ALE)
dz(RD-AD)
d(BCLK-AD)
h(BCLK-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-RD)
h(BCLK-RD)
d(AD-ALE)
h(ALE-AD)
d(BCLK-WR)
h(BCLK-WR)
d(DB-WR)
h(WR-DB)
h(BCLK-DB)
8 /
B
Symbol
0
0
0
1
A
8
G
u
7
o r
. g
0 -
t
t
t
t
t
t
t
t
u
h(RD – AD)
h(RD – CS)
d(AD – ALE)
h(ALE – AD)
1
h(WR – AD)
h(WR – CS)
d(DB – WR)
h(WR – DB)
0
p
0
, 2
0
(with wait, accessing external memory, multiplex bus area selected)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output hold time (BCLK standard)
ALE signal output hold time (BCLK standard)
Address output flowting start time
Address output delay time
Chip select output delay time
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
ALE signal output delay time (BCLK standard)
ALE signal output delay time (address standard)
ALE signal output hold time (address standard)
2
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
WR signal output delay time
DB signal output hold time (BCLK standard)
specified)
0
0
5
=
=
=
=
=
=
Page 256
=
=
10 X m
f
f
f
f
f
f
f
(BCLK)
(BCLK)
f
(BCLK)
(BCLK)
(BCLK)
(BCLK)
(BCLK)
(BCLK)
9
10
10
10
10
10
10
10
9
9
X 2
X 2
9
9
9
9
9
X 2
X 2
X 2
X 2
X 2
Parameter
X 2
f o
3
2
9
– 40
– 20
– 20
– 20
– 20
– 20
– 27
– 20
[ns]
[ns]
[ns]
[ns]
[ns]
[ns]
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
[ns]
CC
= 3V, V
SS
= 0V at Topr = 25
Measuring condition
Figure 28.1
28. Electrical characteristics
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
o
C unless otherwise
– 2
Min.
– 3
0
Standard
0
0
0
Max.
25
25
25
25
25
8
V
CC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 3V