R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 422
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Section 7 DMA Controller (DMAC)
7.5.11
DMAC internal-to-external dual address transfers and single address transfers can be executed at
high speed using the write data buffer function, enabling system throughput to be improved.
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfer and internal accesses
(on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are
independent of the bus mastership, and DMAC dead cycles are regarded as internal accesses.
A low level can always be output from the TEND pin if the bus cycle in which a low level is to be
output from the TEND pin is an external bus cycle. However, a low level is not output from the
TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal
bus cycle, and an external write cycle is executed in parallel with this cycle.
Figure 7.32 shows an example of dual address transfer using the write data buffer function. The
data is transferred from on-chip RAM to external memory.
Page 392 of 1372
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function
Internal read signal
External address
Internal address
Write Data Buffer Function
HWR, LWR
TEND
φ
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
H8S/2426, H8S/2426R, H8S/2424 Group
DMA
read
REJ09B0466-0350 Rev. 3.50
DMA
write
DMA
dead
Jul 09, 2010
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