R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 305
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
R4F24268NVRFQV
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Renesas Electronics America
Quantity:
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H8S/2426, H8S/2426R, H8S/2424 Group
Section 6 Bus Controller (BSC)
6.8.14
Mode Register Setting of Synchronous DRAM
To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to
RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After
that, access the continuous synchronous DRAM space in bytes. When the value to be set in the
synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register
by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus
configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of
address H'400000 + 2X for 16-bit bus configuration synchronous DRAM.
The value of the address signal is fetched at the issuance time of the MRS command as the setting
value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the
synchronous DRAM is not supported by this LSI. For setting the mode register of the synchronous
DRAM, set the burst read/single write with the burst length of 1. Figure 6.71 shows the setting
timing of the mode in the synchronous DRAM.
T
T
T
T
p
r
c1
c2
φ
SDRAMφ
Address bus
Mode setting value
Mode setting value
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
NOP
MRS
NOP
Figure 6.71 Synchronous DRAM Mode Setting Timing
REJ09B0466-0350 Rev. 3.50
Page 275 of 1372
Jul 09, 2010
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