R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 210
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Bus Controller (BSC)
Note:
Page 180 of 1372
Bit
10
9
8
7 to 4 ⎯
3
2
1
0
Bit Name
⎯
RCD1
RCD0
CKSPE*
⎯
RDXC1*
RDXC0*
*
Not supported by the H8S/2426 Group and H8S/2424 Group.
0
0
0
All 0
0
0
0
0
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
RAS-CAS Wait Control
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle. A 1- to 4-state wait cycle can be inserted.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
Clock Suspend Enable
Enables clock suspend mode for extend read data
during DMAC and EXDMAC single address
transfer with the synchronous DRAM interface.
0: Disables clock suspend mode
1: Enables clock suspend mode
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Read Data Extension Cycle Number Selection
Selects the number of read data extension cycle
(Tsp) insertion state in clock suspend mode.
These bits are valid when the CKSPE bit is set to
1.
00: Inserts 1 state
01: Inserts 2 state
10: Inserts 3 state
11: Inserts 4 state
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
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