R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 1083
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2426, H8S/2426R, H8S/2424 Group
19.4.3
The connection between data input/output pins and the SS shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 19.3
shows the relationship.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 19.3 (1)). The SSU
transmits serial data from the SSI pin and receives serial data from the SSO pin when operating
with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 19.3 (2)).
The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode
when operating with BIDE = 1 (bidirectional mode) (see figures 19.3 (3) and (4)).
However, even if both the TE and RE bits are set to 1, transmission and reception are not
performed simultaneously. Either the TE or RE bit must be selected.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function
as an input pin when MSS = 0 (see figures 19.3 (5) and (6)).
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Figure 19.3 Relationship between Data Input/Output Pins and the Shift Register
(1) When SSUMS = 0, BIDE = 0 (standard mode),
(4) When SSUMS = 0, BIDE = 1 (bidirectional mode),
(5) When SSUMS = 1 and MSS = 1
MSS = 1, TE = 1, and RE = 1
MSS = 1, and either TE or RE = 1
Relationship between Data Input/Output Pins and Shift Register
Shift register
Shift register
Shift register
(SSTRSR)
(SSTRSR)
(SSTRSR)
SSCK
SSO
SSI
SSCK
SSO
SSI
SSCK
SSO
SSI
(2) When SSUMS = 0, BIDE = 0 (standard mode),
(3) When SSUMS = 0, BIDE = 1 (bidirectional mode),
(6) When SSUMS = 1 and MSS = 0
Section 19 Synchronous Serial Communication Unit (SSU)
MSS = 0, TE = 1, and RE = 1
MSS = 0, and either TE or RE = 1
Shift register
Shift register
Shift register
(SSTRSR)
(SSTRSR)
(SSTRSR)
Page 1053 of 1372
SSCK
SSO
SSI
SSCK
SSO
SSI
SSCK
SSO
SSI
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