R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 1044
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Section 17 A/D Converter
17.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 17.6 shows the A/D conversion timing. Tables 17.5 and 17.6
show the A/D conversion time.
As shown in figure 17.6, the A/D conversion time (t
time (t
write access to ADCSR. The total conversion time therefore varies within the ranges indicated in
tables 17.5 and 17.6.
In scan mode, the values given in tables 17.5 and 17.6 apply to the first conversion time. The
values given in table 17.7 apply to the second and subsequent conversions. In either case, bit
EKCKS in ADCSR, and bits CKS1 and CKS0 in ADCR should be set so that the conversion time
is within the ranges indicated by the A/D conversion characteristics.
Page 1014 of 1372
D
) and the input sampling time (t
Input Sampling and A/D Conversion Time
Address
Write signal
Input sampling
timing
ADF
φ
[Legend]
(1):
(2):
t
t
t
D:
SPL
CONV
:
: A/D conversion time
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
Figure 17.6 A/D Conversion Timing
(1)
(2)
t
D
SPL
). The length of t
t
SPL
D
) passes after the ADST bit in ADCSR is set to
CONV
t
CONV
) includes the A/D conversion start delay
D
varies depending on the timing of the
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
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