DF2117VT20HV Renesas Electronics America, DF2117VT20HV Datasheet - Page 701
DF2117VT20HV
Manufacturer Part Number
DF2117VT20HV
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VT20HV.pdf
(1040 pages)
Specifications of DF2117VT20HV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VT20HV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2117VT20HV
Manufacturer:
Renesas Electronics America
Quantity:
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20.3.19 Host Interface Select Register (HISEL)
HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt
request signal of each frame.
Bit
7
6
5
4
3
2
1
0
Bit Name
SELSTR3
SELIRQ11
SELIRQ10
SELIRQ9
SELIRQ6
SELSMI
SELIRQ12
SELIRQ1
Initial
Value
0
0
0
0
0
0
1
1
Slave Host Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Status Register 3 Selection
Selects the function of bits 7 to 4 in STR3 in
combination with the TWRE bit in LADR3L. For
details of STR3, see section 20.3.12, Status
Registers 1 to 4 (STR1 to STR4).
0: Bits 7 to 4 in STR3 indicate processing status of
1: [When TWRE = 1]
Host IRQ Interrupt Select
These bits select the state of the output on the
SERIRQ pins.
0: [When host interrupt request is cleared]
1: [When host interrupt request is cleared]
the LPC interface.
Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
[When TWRE = 0]
Bits 7 to 4 in STR3 are readable/writable bits
which user can use as necessary
SERIRQ pin output is in the Hi-Z state
[When host interrupt request is set]
SERIRQ pin output is low
SERIRQ pin output is low
[When host interrupt request is set]
SERIRQ pin output is in the Hi-Z state.
Rev. 2.00 Sep. 28, 2009 Page 659 of 994
REJ09B0452-0200
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