M30281F8HP#U3B Renesas Electronics America, M30281F8HP#U3B Datasheet - Page 100
M30281F8HP#U3B
Manufacturer Part Number
M30281F8HP#U3B
Description
IC M16C/28 MCU FLASH 64K 64LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30281F8HP#U3B
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30281F8HP#U3BM30281F8HP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
1
. v
Figure 9.7 Stack Status Before and After Acceptance of Interrupt Request
J
6
0
9.4.3 Saving Registers
C
2
9
2 /
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 9.7 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
0 .
B
Address
0
0
8
0
m – 4
m – 3
m – 2
m – 1
m + 1
Stack status before interrupt request
is acknowledged
m
G
4
J
7
a
o r
MSB
0 -
. n
u
2
3
p
0
, 1
Content of previous stack
Content of previous stack
0
(
M
2
0
1
0
6
7
C
Stack
2 /
, 8
page 78
M
1
6
C
2 /
f o
LSB
8
3
) B
8
5
[SP]
SP value before
interrupt request is
accepted.
Address
m – 4
m – 3
m – 2
m – 1
m
m + 1
Stack status after interrupt request
is acknowledged
MSB
Content of previous stack
Content of previous stack
FLG
H
Stack
PC
PC
FLG
M
L
L
PC
H
LSB
[SP]
New SP value
9. Interrupts
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