HD64F3672FY Renesas Electronics America, HD64F3672FY Datasheet - Page 67
HD64F3672FY
Manufacturer Part Number
HD64F3672FY
Description
IC H8 MCU FLASH 16K 48QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3672FXV.pdf
(334 pages)
Specifications of HD64F3672FY
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.
A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared
by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling
starts. Exception handling is the same as exception handling by the RES pin.
Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction
generates a vector address corresponding to a vector number from 0 to 3, as specified in the
instruction code. Exception handling can be executed at all times in the program execution state.
External interrupts other than NMI and internal interrupts other than address break are masked by
the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the
current instruction or exception handling ends, if an interrupt request has been issued.
Reset
Trap Instruction
Interrupts
Section 3 Exception Handling
Rev.4.00 Nov. 02, 2005 Page 41 of 304
Section 3 Exception Handling
REJ09B0143-0400
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