MC908QB8CPE Freescale Semiconductor, MC908QB8CPE Datasheet - Page 170
MC908QB8CPE
Manufacturer Part Number
MC908QB8CPE
Description
IC MCU 8BIT 8K FLASH 16-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QB8CDWE.pdf
(236 pages)
Specifications of MC908QB8CPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
For Use With
DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Serial Peripheral Interface (SPI) Module
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of SS from creating a MODF error. See
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See
of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN
bit is 0 for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. When MODFEN is 1, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
User software can read the state of the SS pin by configuring the appropriate pin as an input and reading
the port data register. See
15.8 Registers
The following registers allow the user to control and monitor SPI operation:
170
•
•
•
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
1. X = Don’t care
SPE
0
1
1
1
A high on the SS pin of a slave SPI puts the MISO pin in a high-impedance
state. The slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
MASTER SS
MISO/MOSI
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
SPMSTR
X
0
1
1
(1)
Table 15-2.
MODFEN
BYTE 1
Figure 15-12. CPHA/SS Timing
Table 15-2. SPI Configuration
MC68HC908QB8 Data Sheet, Rev. 3
X
X
0
1
Master without MODF
SPI Configuration
Master with MODF
NOTE
Not enabled
Slave
BYTE 2
15.8.2 SPI Status and Control Register.
15.3.6.2 Mode Fault
General-purpose I/O;
General-purpose I/O;
Function of SS Pin
SS ignored by SPI
SS ignored by SPI
BYTE 3
Input-only to SPI
Input-only to SPI
Freescale Semiconductor
Error.) For the state
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